Knowledge, Skills & Abilities:
• Strong understanding of SoC RTL integration and the tradeoffs required to map large designs onto prototyping and emulation platforms.
• Hands-on experience with FPGA prototyping and hardware emulation platforms such as HAPS, ZeBu, or similar Cadence/Siemens/Synopsys environments. • Experience with Static timing analysis for XILINX/Intel FPGA platforms
• Familiarity with ARM Cortex-M/R/A architectures, SoC peripherals, and system interfaces such as LPDDR/DFI, eMMC, PCIe, JTAG/SWD, UART, SPI, I2C/I3C, GPIO, and QSPI Flash.
• Experience debugging clocks, resets, timing issues, waveforms, platform bring-up problems, and embedded software crashes or asserts across multiple pre-silicon targets.
• Ability to work from RTL, hardware schematics, datasheets, and timing reports, and to communicate platform limitations and integration constraints clearly across hardware and software teams.
• Strong problem-solving, communication, teamwork, and prioritization skills in a fast-paced cross-functional environment.
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years of experience in SoC prototyping, FPGA/emulation bring-up or pre-silicon validation.
• Experience with RTL integration, FPGA prototyping, hardware emulation, or pre-silicon validation.