· Digital Architecture and Design: Architect and design digital blocks and subsystems of complex high-speed SerDes ICs, including Gigabit‑speed serial interfaces and video and data routing solutions.
· Develop Next‑Generation Technologies: Drive the evolution of OpenGMSL technology through the development of new architectures, authoring and advancing of OpenGMSL technical standards, and active participation in industry standards organizations and committees.
· Specification Ownership: Write detailed block and subsystem-level specifications for design and implementation.
· RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems, and top‑level designs.
· Verification and Coverage Closure: Develop block‑level testbenches, verify block functionality, and collaborate with verification teams to achieve full‑chip verification and coverage closure.
· Digital Backend: Perform block‑ and top‑level linting, CDC analysis, and power analysis. Assist with synthesis constraints and timing closure.
· Mixed‑Signal Integration: Communicate closely with mixed-signal designers and verification engineers to support mixed‑signal simulations and real‑number modeling across the analog/digital boundary.
· Documentation and Design Reviews: Prepare technical documentation and lead architecture, design, and peer reviews.
· Lab Evaluation and Debug: Support silicon bring‑up, characterization, and debug activities.
· Cross‑Functional Collaboration: Collaborate across analog, digital, verification, test, and product definition teams to define requirements, support production test development, and ensure successful product execution.
· Technical Leadership: Provide technical leadership for complex SerDes subsystems and products.