● Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, VLSI, or a related discipline.
● Experience with timing sign-off for chiplet-based designs, multi-die architectures, or advanced package-based silicon platforms.
● Good understanding of physical design implementation, floorplanning, placement-aware synthesis, clock tree synthesis, routing, and physical timing closure.
● Experience with signal integrity, crosstalk, noise analysis, timing derates, OCV/AOCV/POCV, and advanced timing variation methodologies.
● Familiarity with DFT timing, scan modes, OCC, test constraints, MBIST/LBIST timing, and test-mode closure.
● Experience developing synthesis and timing closure methodologies for cost-sensitive and high-performance designs.
● Experience evaluating EDA tools, improving implementation recipes, and driving quality-of-results improvements.
● Ability to propose innovative and leading-edge solutions for timing closure, synthesis optimization, and design convergence.
● Track record of driving complex technical issues to closure with attention to detail and strong ownership.
● Experience with 2nm, 3nm, or other leading-edge process technologies.
● Experience with chiplet-based designs, advanced packaging, inter-die interfaces, or multi-die timing closure.
● Knowledge of AI/HPC architectures, processor pipelines, vector processing units, NoC fabrics, or memory subsystem timing challenges.
● Experience with physical-aware synthesis, congestion-aware optimization, placement-aware timing analysis, and PPA correlation.
● Familiarity with sign-off quality checks including timing, power, signal integrity, noise, transition, capacitance, and clock quality.
● Exposure to silicon bring-up, timing correlation, production support, and post-silicon debug.
● Experience driving methodology improvements, EDA automation, and flow standardization across teams.
● Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.
● Can-do attitude, openness to new environments, people, and cultures.
● Passion for solving complex timing and implementation challenges while delivering high-quality silicon under aggressive schedules.
● Background in RTL-to-gate synthesis and implementation; Static Timing Analysis and timing sign-off; multi-mode multi-corner timing closure; constraint development and validation; compute, CPU, VPU, AI accelerator, and
high-performance digital IP implementation; low-power synthesis and power-aware timing closure; UPF/CPF-based power intent implementation; hierarchical timing closure and full-chip timing convergence; timing ECO,
functional ECO, and late-stage design closure; EDA flow automation and synthesis/STA methodology development; or cross-functional silicon development with RTL, DFT, physical design, CAD, verification, and product engineering teams.