Develop and execute validation plans, test cases, and debug strategies for functional and system-level validation.
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Lead hardware debug and failure analysis by performing root cause investigations of boot failures, system hangs, data corruption, memory access issues, and intermittent hardware failures.
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Validate and debug interfaces such as PCIe, Ethernet, CAN/CAN FD, LIN, FlexRay, UART, I2C, and SPI.
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Perform Lab Validation & debugging using oscilloscopes, logic analyzers, protocol analyzers, bus sniffers, and JTAG.
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Validate SRAM/Flash and debug memory initialization, access, and data integrity issues.
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Read schematics and perform pin-level signal tracing to isolate hardware issues.
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Work with RTL/design, firmware, architecture, and system teams to identify root causes and drive issues to closure.
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Lead technical debug activities and mentor validation engineers.
Job Complexity:
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Leads technical execution of silicon validation and hardware debug activities.
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Provides technical guidance on silicon bring-up, validation, failure analysis, and debug methodologies.
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Review validation plans, test methodologies, and debug approaches.
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Coordinates with cross-functional teams to resolve complex silicon and system-level issues.
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Drive issue tracking, validation metrics, and closure activities.
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Mentor junior engineers on silicon debug and validation best practices.
What Are We Looking For
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10-15 years of strong hands-on expertise in silicon bring-up, board-level debugging, protocol validation, hardware failure analysis, and lab-based validation on real silicon platforms.
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Strong experience with SoC, MCU, or ASIC bring-up and functional validation.
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Hands-on experience with power, reset, clocking, straps, configuration errors.