Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).
Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.
Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.
Perform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.
Methodology and Automation
Develop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).
Proactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.
Evaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.
Technical Leadership & Team Enablement
Provide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.
Mentor junior engineers and NCGs in PNR, STA and debug practices to build a strong second tier of technical capability.
Review floorplans, constraints, and implementation choices from team members, giving clear, actionable feedback.
Act as a go-to technical reference within the PD team.
Cross-Functional Collaboration
Work closely with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints.
Communicate risks, options, and trade-offs clearly to project leads and managers, and help shape mitigation plans.
Participate in design reviews and signoff reviews, representing physical design status, risks, and recommendations.