Epia Neuro is a neural technology company developing intent-driven systems designed to restore function and independence for people living with neurological conditions. Its platform integrates implantable neural interfaces, adaptive algorithms, and assistive devices to translate neural intent into real-world action. The company’s initial focus is stroke-related motor impairment, with expansion in cognitive decline and other neurological disorders, focusing on long-term solutions for the growing aging population.
The Role
We’re looking for an ASIC Design Engineer who wants to be involved in all aspects of design cycle: documentation, design, pre-silicon verification, and post-silicon validation.
The team is small in a startup environment, so the role is dynamic and all efforts will have visible impact. You’ll work alongside senior engineers across all disciplines of ASIC design and have ownership from day one. Ideal candidate is inquisitive and a creative problem solver, who likes to tinker with whatever resources available.
Location
This role is expected to work on site from our Alameda Headquarters 5 days a week.
What You’ll Do
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Document and implement module designs
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Simulate module functions and support pre-silicon verification
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Build/develop test HW/SW to validate chips
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Validate and characterize chips across configurations
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Document test plans and test reports
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Root-cause issues beyond surface-level symptoms
Qualifications
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Bachelor’s degree in Electrical Engineering/Computer Science, plus relevant industry experience in ASIC design — or a Master’s/PhD with hands-on ASIC design experience through university lab or project work
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Strong written and verbal communication skills — you’ll need to document your work clearly and communicate project status, good or bad
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Comfortable working independently in a Linux/Linux-like environment, working with open-source projects