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Fractile

Lead Physical Design Engineer

LocationBristol - The Crescent, London - The Record Hall, Bristol
Work modeon-site
Typefull-time
DepartmentSilicon
EquityIncluded
Company size51–200 people
First seen1w ago
Last seen13h ago
Lead Physical Design Engineer
About Fractile
Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.
The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.
We are seeking a highly skilled Lead Physical Design Engineer to contribute to our next-generation chip designs. As a Lead Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off. In this role, you will take on leadership responsibilities across multiple dimensions, including full-chip ownership, leading a team of physical design engineers, and contributing to broader chip-level physical design leadership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.
Key Responsibilities:
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Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
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Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.
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Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
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Own power planning and analysis, addressing IR drop, electromigration, and related effects.
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Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
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Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
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Develop and improve flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
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Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
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Mentor junior engineers and contribute to building strong physical design practices across the team.
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Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Proven ability to take ownership of complex designs and drive them to completion.
• Experience mentoring engineers and leading physical design efforts.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.
How we work:
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Ownership and execution: you will have full agency to drive your work forward
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Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
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Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
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Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
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Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped
What We Offer
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Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.
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Equity & Ownership: meaningful equity so everyone shares in the value creation.
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Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.
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Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment.
Fractile is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us!
Export controls
Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We’ll be transparent about this throughout the hiring process.
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