Bachelor’s degree in electronic engineering, Computer Engineering or in a related field
Technical Skills
• 3+ years of experience in semiconductor failure analysis or test engineering
• Strong understanding of Array architecture and failure mechanisms or hands-on experience with SCAN ATPG methodology, including Scan chain diagnosis, ATPG pattern generation and debug, Fault models (stuck-at, transition, path delay, bridging)
• Proficiency in fault isolation techniques, including Electrical fault isolation (EFI), circuit, and layout analysis
• Familiarity with failure signature analysis and yield learning
Debug and Analysis
• Experience debugging logic and memory/array failures from silicon bring-up through production
• Ability to correlate ATE test results with design and process data
• Experience with tester platforms (e.g., Advantest, Teradyne)
• Understanding of DFT (Design for Testability) concepts and implementation
Preferred Qualifications
• Experience with embedded memory compilers and array redundancy analysis
• Familiarity with statistical data analysis tools (JMP, Python, R)
• Experience with nanometer process nodes (7nm, 5nm, 3nm, or below)
• Background in BIST (Built-In Self-Test) for memory and logic
• Exposure to machine learning-based fault classification or yield analysis
• Experience collaborating with design, process, and layout teams for root cause analysis
Soft Skills and Work Style
• Strong analytical and problem-solving skills
• Ability to work in a fast-paced, cross-functional environment
• Excellent communication skills to present findings to engineering and management teams
• Self-motivated with ability to manage multiple debug cases simultaneously
• Team player with experience working across design, process, and manufacturing organizations