● Lead RTL development across key portions of the Velaura SoC.
● Collaborate with architects to translate system requirements into robust microarchitectures.
● Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture.
● Partner closely with software teams to define programming models, execution flows, memory hierarchies, and performance-critical interfaces.
● Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure.
● Develop high-quality, power-efficient, and scalable RTL implementations.
● Conduct architecture and RTL reviews to ensure performance, power, and area goals are achieved.
● Work closely with performance modeling, verification, physical design, and software teams throughout the development cycle.
● Help establish engineering processes and design methodologies as the organization grows.
● Mentor and develop other RTL engineers.