Experience
∙ 5+ years of experience in die design and physical layout engineering
∙ Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent)
∙ Proven experience with TSV-based die design including KOZ management, micro-bump layout, and backside RDL
Technical Skills
∙ Deep expertise in physical design and layout using industry-standard EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler)
∙ Strong knowledge of DRC/LVS/ERC sign-off flows and foundry PDK rule interpretation
∙ Solid understanding of TSV design rules, stress modeling implications, and 3D integration layout constraints
∙ Working knowledge of DFT structures relevant to advanced packaging: daisy chains, BIST, boundary scan, IEEE P1838
∙ Familiarity with JEDEC HBM specifications (HBM2E, HBM3, HBM3E)
∙ Understanding of power integrity, signal integrity, and thermal considerations at the die-package interface
∙ Experience with parasitic extraction and layout-driven optimization for high-speed memory interfaces