● Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
● Understanding of transistor-level circuit design and PPA optimization for standard cells including latches, flip-flops, multiplexers, AOI/OAI, XOR/XNOR, encoders, decoders, level shifters, and arithmetic cells.
● Strong understanding of Layout Dependent Effects (LDE), advanced-node device physics, and manufacturing-aware design.
● Good understanding of Static Timing Analysis (STA), Liberty (.lib) modeling, and flip-flop timing.
● Knowledge of ASIC implementation and sign-off methodologies.
● Programming and automation experience using Python, Tcl, or Perl.
● Experience with low-power library characterization and advanced Liberty modeling features.
● Exposure to custom circuit design and standard cell layout optimization.
● Excellent communication, collaboration, analytical, and problem-solving skills, with a strong sense of ownership and the ability to deliver under demanding project schedules.
● Background in standard cell characterization and library development; timing, power, and noise model generation; advanced-node technologies including Deep Submicron, FinFET, and GAA; or statistical characterization and model
validation.