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Member of Technical Staff, AI-Driven Compilation

Salary$275k – $315k

LocationSan Francisco

Work modeon-site

Typefull-time

DepartmentResearch

EquityIncluded

Company size1+ people

First seen2w ago

Last seen2d ago

At SF Tensor, we’re building the future of high-performance compute

We firmly believe that the future of AI depends on the unglamorous: rethinking and rebuilding the stack, all the way down. From the hardware underneath it to the compiler targeting it and the cloud running it. Right now those three things fight each other and that friction shows up as a tax on every researcher trying to build something ambitious. We’re here to axe that tax and make compute faster, cheaper and more available. When we succeed, compute will be portable enough that “which cloud, which chip” stop being something you worry about.

To achieve this, we are building our Kernel Optimizer, which takes code and finds its fastest possible form for whatever vendor and cluster topology you point it at, automatically, as well as the Model Foundry which manages the runs, makes research easier and moves workloads across clouds and chips as prices and availability ship, instead of leaving you locked into whatever vendor you signed with first.

We’re backed by Susa Ventures, Y Combinator, along with some great funds and angels including Max Mullen and Paul Graham, as well as founders and executives at Neuralink, Notion and AMD. We’re looking for researchers, engineers and organizations who agree with the basic premise: you don’t get the next leap in AI without a leap in compute first.

About the Role

We build the fastest GPU compiler in the world. Most compilers have to preserve correctness at every transform, constraining how far they can search, while we prove correctness at the end instead, allowing us to search a far wider space, with agents, with RL, with anything that works and still guarantee the result. It’s why we hold #1 on NVIDIA’s own kernel benchmark across hundreds of production kernels.

We’re hiring a Member of Technical Staff for AI-Driven Compilation to own the search itself. Proving correctness at the end is what makes the search legal and your job is to make it good.

You’ll be building the agentic and RL systems that decide which programs are worth trying (instruction selection, scheduling, barriers and stall counts, tiling, fusion, phase ordering) over a space that is enormous precisely because nothing in it has to be conservative.

The reward signal here is unusually clean for RL: measure wall-clock on real silicon gated by a formal proof. No proxy metrics, no reward hacking that survives contact with the verifier. The system already does things worth seeing. Given only a naive attention spec, the search found FlashAttention v4-level performance on a B300 in about 25 minutes, but it also generalizes. The same loop runs on AMD, TPU and Trainium as well as targets we’d never seen before, such as Apple Silicon.

You’ll have access to better tooling than anywhere else because we own the stack all the way down to the ISA, allowing us to create kernels that others can’t even express. For example, our custom LLVM backend emits cubins directly, without ptxas, letting us work on instruction selection, scheduling, register allocation and stall counts. Our team understands the hardware better than anyone else, to this extent we’ve built a bit-exact software model of Blackwell’s tcgen05.

The kernels you create will ship immediately on runs such as pre-training AlphaFold v3 at 3.4× the throughput, post-training robotics models on Trainium or running our custom RL rollout engine on TPU at multi-100B parameter scale.

What You’ll Do

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You’ll design and implement RL systems that search over a massive program space: instruction selection, schedules, tile sizes, fusion strategies and phase ordering

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You’ll build agentic compilation loops that use LLMs to reason about IR, propose transformations and learn from measured results

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You’ll design the search and credit-assignment machinery around an exact reward built from measured latency on real hardware and a formal correctness proof

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You’ll create representations and embeddings of compiler IR that hold up under learned optimization

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You’ll build the training infrastructure for compiler optimization agents, including rollout throughput and distributed evaluation on real silicon

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You’ll push transfer and cold-start performance so that the search works on unfamiliar targets and new ISAs from the first trial

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You’ll close the loop with production workloads so that the compiler keeps improving from what customers actually run

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You’ll work directly with our compiler and kernel engineers to land learned components in the shipping pipeline

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You’ll run rigorous experiments, dig into the results, iterate on them and publish or open-source some of them

What We’re Looking For

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Someone with a strong background in reinforcement learning with hands-on experience training agents

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Someone with experience building LLM agents, tool use and other agentic systems

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Someone with familiarity in GPU programming concepts and a willingness to get down to the ISA

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Someone proficient in PyTorch or JAX

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Someone with the ability to design and run experiments that produce trustworthy results

Nice to Have

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Someone with experience in ML compiler stacks (XLA, TVM, Triton, MLIR) or LLVM backends

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Someone with a background in program synthesis, superoptimization, combinatorial search, formal methods, SMT solvers or verified compilation

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Someone familiar with RLHF, reward modeling or preference learning

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Someone with research contributions in RL or learned optimization

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Someone familiar with GPU performance optimization, profiling and microbenchmarking

Why Join Us

Compiler optimization is the rare place where a learned system gets an enormous action space and a ground-truth reward at the same time. What usually blocks this work is everything around it (a background that can’t execute what the search finds or no way to trust the result). You get both here: direct cubin emission below ptxas and a prover that tells you whether the program is correct. In this role, you’ll have the tools and researches to let your most ambitious research ideas run wild and if they find valid kernels, ship them into production in days rather than becoming a paper and then nothing.

We’re a small team operating at frontier scale. We pre-trained foundation models on 4,000 AMD GPUs as a team of three, designed and brought up GB300 NVL72 clusters and designed a TOP500 supercomputer.

We believe that hard problems get solved in person and most of our work happens at our office in San Francisco. We offer relocation assistance and, where possible, we’d like you here as often as possible.

The base salary range for this full-time position is $275,000-$315,000, plus meaningful equity and benefits.

More roles at SF Tensor

Member of Technical Staff, GPU Compiler Member of Technical Staff, GPU Kernels Member of Technical Staff, Product Engineering Member of Technical Staff, Sandbox Infrastructure Member of Technical Staff, Post-Training & Applied Research

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