● Design, implement, and optimize RTL for key portions of the Velaura SoC.
● Collaborate with architects to develop robust and efficient microarchitectures.
● Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
● Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
● Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
● Optimize designs for performance, power, area, scalability, and reliability.
● Partner closely with verification and physical design teams throughout the development cycle.
● Analyze performance bottlenecks and propose architectural and implementation improvements.
● Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
● Participate in design reviews and contribute to a culture of technical excellence.