Head of Memory Architecture (Xora Portfolio Company)
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Before you apply
SalaryNo pay range posted
LocationSan Jose, California, United States
Typefull-time
SeniorityDirector
Experience10+ yrs
DepartmentXVL
Company size10+ people
PostedOct 12, 2026 · 3w ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
10+ years in memory architecture, preferably the leading memory IDMs
Deep grasp of state-of-the-art memory issues and challenges particularly associated with Agentic AI inference computing
Power, performance, area and cost (PPAC) analysis and modeling
Broad network of relevant industry and academia experts to deepen our understanding and to evangelize our memory offering
M.S. or Ph.D. in Computer Science (CS), Computer Engineering (CE), or Electrical Engineering (EE) preferred
Skills
memory architecture
PPAC analysis
SOC architectures
on-chip interconnects
sense amplifiers
ABOUT THE COMPANY
We are a Silicon Valley, San Jose based stealth start-up and are looking for a passionate, ambitious individual who shares our vision of next generation disruptive memory solutions for Agentic AI inference and high performance data center computing applications.
About the role
This is an impactful and senior leadership role allowing you to mastermind the realization of our strategic ambitions and shape the direction of our product portfolio development.
ABOUT THE ROLE
In your role as Head of Memory Architecture, you will lead the architectural design of our disruptive product which is a purpose-built memory for AI inference computing, building on your extensive knowledge and industry experience combined with our proprietary in-house device technology capabilities. It is a senior engineering role responsible for designing, modeling, and optimizing the memory subsystems for a new memory category and product for AI inference computing. Close collaboration with device technology and commercial development teams is an essential element of this role.
CORE RESPONSIBILITIES
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Architecture & Trade-off Analysis: Balance memory footprint, bandwidth, latency, power efficiency, density, silicon area, and cost/bit.
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Subsystem Design: Design memory vaults and hierarchies, on-chip interconnects, sense amplifiers and address translation with emphasis on high granularity and bandwidth
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Workload Optimization: Analyze state-of-the-art Agentic AI inference applications, software, AI inference models, leading edge SOCs for data center workloads and how they interact with memory to reduce bottlenecks. Benchmark leading edge AI inference SOC architectures and workload management specifics vis a vis competing memory architectures and devices including our disruptive memory solution.
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Novel Bit Cell and Device Architectures: Ability to understand and leverage our core materials and device technology to realize a category defining memory for inference computing
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Cross-Functional Collaboration: Partner with SOC architects, NPI teams, silicon design and technology teams to drive acceleration of the product to market.
REQUIRED QUALIFICATIONS & SKILLS
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Education: M.S. or Ph.D. in Computer Science (CS), Computer Engineering (CE), or Electrical Engineering (EE) preferred.
•
Experience: 10+ years in memory architecture, preferably the leading memory IDMs.
•
Technical Knowledge:
•
Deep grasp of state-of-the-art memory issues and challenges particularly associated with Agentic AI inference computing.
•
Power, performance, area and cost (PPAC) analysis and modeling.
•
Network Connections: Broad network of relevant industry and academia experts to deepen our understanding and to evangelize our memory offering.