SoC Verification Senior Lead Engineer
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Before you apply
LocationBangalore
Typefull-time
SeniorityLead
Experience12–15 yrs
Company size10,000+ people
PostedOct 22, 2026 · 2w ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
12-15 years in SoC/IP verification with participation in successful tape-outs of SoCs
Strong expertise in ARM-based microcontrollers and SoC-level verification, including C based DV
Proficiency in Verilog, SystemVerilog, UVM, and constrained-random verification
Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium)
Experience with low-power verification (UPF) is a must
Gate-level simulations and power-aware simulations is a must
Good working knowledge of assertions (SVA) and functional coverage
Comfortable working in a fast-paced environment
Strong team player with excellent communication skills
Bachelors or Master's in Microelectronics, Electronics, Electrical Engineering
Verification of multiple interfaces: SPI, I2C, UART, CAN, eSPI is desirable
Knowledge of Flash memory and security IPs is nice to have
Any experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage
Skills
Verilog
SystemVerilog
UVM
C
Synopsys VCS
Cadence Xcelium
UPF
SVA
SPI
I2C
UART
CAN
eSPI
Flash memory
Role Overview:
We are seeking an experienced Verification Engineer with 12+ years of experience for execution of SoC verification of complex SoCs. The ideal candidate will have deep knowledge of ARM-based microcontrollers, low-power design verification, and experience with multiple interfaces and security IPs. This is a hands-on role requiring strong technical skills and collaboration in a fast-paced environment.
Key Responsibilities:
•
Develop and own SoC-level and/or IP-level verification suites with coverage goals.
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Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
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Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
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Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage
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Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
•
Good understanding of formal verification techniques and methodologies.
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Familiar with both SoC-level and IP-level verification environments.
•
Collaborate with the team in developing and improving flows for maximum reuse and efficiency.
•
Mentor junior team members while actively collaborating with design teams for issue resolution and sign-off.
Required Qualifications:
•
Experience: 12-15 years in SoC/IP verification with participation in successful tape-outs of SoCs.
•
Technical Skills:
•
Strong expertise in ARM-based microcontrollers and SoC-level verification, including C based DV.
•
Proficiency in Verilog, SystemVerilog, UVM, and constrained-random verification.
•
Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium).
•
Experience with low-power verification (UPF) is a must.
•
Gate-level simulations and power-aware simulations is a must.
•
Good working knowledge of assertions (SVA) and functional coverage.
•
Verification of multiple interfaces: SPI, I²C, UART, CAN, eSPI is desirable.
•
Knowledge of Flash memory and security IPs is nice to have.
•
Any experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage.
•
Soft Skills:
•
Comfortable working in a fast-paced environment.
•
Strong team player with excellent communication skills.
•
Education: Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering
About the company
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