Preferred Qualifications
• Expertise in formal verification methodologies and tools (e.g., JasperGold, VC Formal, Questa Formal).
• Strong knowledge of System Verilog Assertions (SVA) and property-based verification.
• Deep understanding of digital design concepts, clock domain crossings, and low-power design techniques.
• Familiarity with UVM-based simulation environments and how formal complements dynamic verification.
• Scripting skills (Python, TCL, Perl) for automation and flow optimization.
• Ability to lead projects, work cross-functionally, and deliver under tight schedules.
• Strong analytical skills, attention to detail, and a collaborative mindset.