Senior Staff / Principal SOC Floorplan Lead
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Before you apply
LocationIndia, Bangalore
Work modeon-site
Typefull-time
SeniorityLead
Experience12+ yrs
DepartmentHardware
EquityIncluded
Company size51–200 people
PostedAug 3, 2026 · 3mo ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
12+ years of hands-on experience in Physical Design SoC Floorplanning preferably in Datacenter domain
At least 3 years acting as a lead or primary owner of SoC-level Floorplanning
Proven track record of taping out large, complex chips for Data Center, Networking, or AI/Machine Learning applications
Highly driven, self-motivated, and comfortable with ambiguity
Deep understanding of how RTL structures and architectural decisions impact physical design PPA
Extensive experience with bump planning, flip-chip package requirements, and die-to-package co-optimization
Strong knowledge of analog/mixed-signal IP integration, shielding, and custom routing constraints
Expertise with industry-standard physical design tools (Cadence Innovus)
BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field
Experience with multi-die / chiplet integration (2.5D, 3D packaging, interposers, UCIe)
Strong scripting and automation skills (Tcl, Python, Perl, Makefile)
Knowledge of advanced clocking architectures (H-trees, meshes) for highly synchronous AI fabrics
Skills
Tcl
Python
Cadence Innovus
Perl
Makefile
Benefits
Equity
The Role
We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA).
If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you.
Key Responsibilities
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Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below).
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Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA.
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Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery.
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Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions.
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Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop.
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Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion.
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Methodology Development: Build and maintain scalable Floorplanning workflows and scripts (Tcl, Python) tailored for a lean, fast-moving start-up team.
Required Skills & Qualifications
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Experience: 12 + years of hands-on experience in Physical Design SoC Floor planning preferably in Datacenter domain, with at least 3 years acting as a lead or primary owner of SoC-level Floorplanning.
•
Domain Expertise: Proven track record of taping out large, complex chips—specifically for Data Center, Networking, or AI/Machine Learningapplications.
•
Start-Up Mentality: Highly driven, self-motivated, and comfortable with ambiguity. You take extreme ownership of your domain, pivot quickly when needed, and roll up your sleeves to get things done.
•
Technical Depth:
•
Deep understanding of how RTL structures and architectural decisions impact physical design PPA.
•
Extensive experience with bump planning, flip-chip package requirements, and die-to-package co-optimization.
•
Strong knowledge of analog/mixed-signal IP integration, shielding, and custom routing constraints.
•
Expertise with industry-standard physical design tools ( Cadence Innovus).
•
Education: BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
Preferred Qualifications
•
Experience with multi-die / chiplet integration (2.5D, 3D packaging, interposers, UCIe).
•
Strong scripting and automation skills (Tcl, Python, Perl, Makefile).
•
Knowledge of advanced clocking architectures (H-trees, meshes) for highly synchronous AI fabrics.
What We Offer
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Impact: The opportunity to build ground-up architecture and see your ideas taped out in cutting-edge silicon.
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Equity: Competitive start-up equity packages—when the company wins, you win.
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Culture: A flat, collaborative, and bureaucracy-free environment surrounded by top-tier industry veterans.