Sr/Staff Engineer, Design Verification,System IP
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Before you apply
LocationBengaluru, Karnataka, India
Work modehybrid
Typefull-time
SeniorityLead
DepartmentRISC V
Company size501–1,000 people
PostedMay 25, 2026 · 5mo ago
Verified live20h ago
May no longer be actively hiring
Posted by the company on May 25, 202643% of this company's open roles have been listed for 90+ days
At a glanceSummarised by Seekless from the posting.
Hands-on experience in ASIC or SoC verification using SystemVerilog and UVM
Enjoy debugging complex design and verification issues
Comfortable building verification environments from scratch and driving coverage closure
Familiarity with standard bus protocols and modern verification tools
Experience owning block or subsystem-level verification from test planning to sign-off
Strong understanding of constrained-random verification, coverage analysis, and regression debugging
Familiarity with protocols such as AXI, ACE, CHI, or PCIe
Scripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements
Applicant must be eligible to access U.S. export-controlled technology
Skills
SystemVerilog
UVM
Python
Perl
TCL
Bash
AXI
ACE
CHI
PCIe
About the company
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
About the role
We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure.
This role ishybrid, based out of Bangalore, India.
Hiring process
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
•
You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM.
•
You enjoy debugging complex design and verification issues and working closely with cross-functional teams.
•
You’re comfortable building verification environments from scratch and driving coverage closure.
•
You have familiarity with standard bus protocols and modern verification tools.
What We Need
•
Experience owning block or subsystem-level verification from test planning to sign-off.
•
Strong understanding of constrained-random verification, coverage analysis, and regression debugging.
•
Familiarity with protocols such as AXI, ACE, CHI, or PCIe.
•
Scripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements.
What You Will Learn
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Verification of advanced CPU and memory-management related IPs used in AI/ML systems.
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Building scalable UVM environments and improving verification methodologies.
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Collaborating across architecture, RTL, and validation teams throughout the development cycle.
•
Using Automation and AI-assisted tools to improve productivity and debug efficiency
Benefits
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Legal
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.