The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.
Strong hands-on experience in Timing Signoff methodology development and ownership.
Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.
Strong hands-on experience with statistical data analysis and modeling.
Strong hands-on experience in silicon technologies, testability and yield.
Strong hands-on experience with industry standard STA tools such as Primetime and Tempus.
Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation.
Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.
Strong analytical skills and extremely detail oriented, organized and methodical.
Strong communication skills. Clear and concise.
Strong multitasking and context switching skills.
Optimistic yet pragmatic attitude.
Demonstrable skills for quick ramp-up.
Ability to stay calm under extreme pressure.
Able to work with minimum supervision, handle ambiguity and drive problem solving to resolution autonomously.