Lead ASIC DFT Engineer
LocationUnited States
Typecontract
SeniorityLead
Company size1,001–5,000 people
PostedJul 22, 2026 · 2mo ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
Strong hands-on experience in ASIC DFT with end-to-end ownership
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation
Proven post-silicon debug and silicon bring-up experience
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges
Strong communication skills
Ability to work independently with minimal ramp-up
Experience with MBIST implementation and verification; SMS experience preferred
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred
Skills
Synopsys
Cadence
Siemens/Mentor EDA
Tessent
SSN
About the role
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield
Requirements
Required Skills & Qualifications
•
Strong hands-on experience in ASIC DFT with end-to-end ownership.
•
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
•
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
•
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
•
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
•
Experience with MBIST implementation and verification; SMS experience preferred.
•
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
•
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
•
Proven post-silicon debug and silicon bring-up experience.
•
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
•
Strong communication skills and the ability to work independently with minimal ramp-up.
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