Digital ASIC Design Engineer
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Before you apply
LocationBethlehem, PA, Menlo Park, California, Nuremberg, Germany, Ottawa, Ontario, Nuremberg, Germany
Work moderemote
Typefull-time
SenioritySenior
Experience5+ yrs
DepartmentProduct Development (300)
Company size51–200 people
PostedOct 7, 2026 · 3w ago
Verified live20h ago
At a glanceSummarised by Seekless from the posting.
5+ years of hands-on experience in CMOS (bulk and FinFET), digital IC design in various process technologies
Proven experience in strong coding/verification in SystemVerilog is required
Scripting language experience: Tcl, Python, and shell scripts
Bus interfaces: PCIe, AXI, UCIe, SPI, I2C, APB
Strong communication and teamwork skills
Bachelor's Degree in Electrical Engineering or related field is required
Master's Degree in Electrical Engineering, Computer Engineering or a related field is preferred
Experience designing high speed Modems, SerDes, DSP blocks, FFTs, clock recovery, carrier recovery, digital filters, CTLE, DFE and MLSE
Experience matching and debugging Matlab models and vectors in RTL/gate level simulations
Experience working on a multidisciplinary team with Systems, RF, Mixed Signal, and SW engineers
Experience with Cadence tools: XCelium, Genus, Tempus, Conformal, and Voltus
Experience delivering IP blocks to internal and external customers
Ability to drive innovation and implement new design methodologies
Skills
SystemVerilog
Tcl
Python
shell scripts
PCIe
AXI
UCIe
SPI
I2C
APB
Cadence Xcelium
Cadence Genus
Cadence Tempus
Cadence Conformal
Cadence Voltus
About the Role
We are seeking an experienced Digital IC Design Engineer to join our growing team. In this role, you will be part of an experienced design team developing cutting-edge DSP and mixed-signal ICs. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals.
Key Responsibilities
•
Flow system level requirements into Architecture and Design Specifications
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Work closely with Comm Systems Engineers to recommend implementation options for best power, performance, and area.
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Document and write RTL code to meet system requirements
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Write SystemVerilog testbenches and testcases to fully verify the design
•
Develop timing constraints, Synthesize the design and perform Static Timing Analysis and Timing Closure.
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Perform gate level simulations.
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Support lab and HW/SW integration post-tapeout
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Collaborate with cross-functional teams to ensure timely project execution and design tape-outs
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Stay updated with the latest trends and technologies in wideband high speed IC design and apply them to improve project outcomes
•
Occasional travel to the Bay Area (<10%) for remote position
Qualifications
Required:
•
5+ years of hands-on experience in CMOS (bulk and FinFET), digital IC design in various process technologies
•
Proven experience in strong coding/verification in SystemVerilog is required
•
Scripting language experience: Tcl, Python, and shell scripts required.
•
Bus interfaces: PCIe, AXI, UCIe, SPI, I2C, APB
•
Strong communication and teamwork skills
Education:
•
Bachelor’s Degree in Electrical Engineering or related field is required
•
Master’s Degree in Electrical Engineering, Computer Engineering or a related field is preferred
Preferred:
•
Experience designing high speed Modems, SerDes, DSP blocks, FFTs, clock recovery, carrier recovery, digital filters, CTLE, DFE and MLSE.
•
Experience matching and debugging Matlab models and vectors in RTL/gate level simulations.
•
Experience working on a multidisciplinary team with Systems, RF, Mixed Signal, and SW engineers
•
Experience with Cadence tools: XCelium, Genus, Tempus, Conformal, and Voltus
•
Experience delivering IP blocks to internal and external customers
•
Ability to drive innovation and implement new design methodologies.
About Attotude
AttoTude is at the forefront of revolutionizing data centers through advanced interconnect technology based on wired THz transceivers. By adapting the fiber from photonics and advancing today’s ASICs to THz, our innovative AttoEngine eliminates networking bottlenecks, enabling high-speed interconnects for AI data centers. We are committed to overcoming existing networking bottlenecks to unleash the full potential of artificial intelligence.
Why Join Us
· Work at the forefront of semiconductor research and innovation in digital communications.
· Collaborate with a multidisciplinary team driving the next generation of THz technology
· Access to state-of-the-art tools and processes at the leading-edge of ASIC development.
· Competitive compensation, professional growth, and opportunities for scientific contribution.