At a glanceSummarised by Seekless from the posting.
Must have6
At least 6-10 years of experience in Low power RTL design, microarchitecture, synthesis, timing closure, power estimation
Proficient in Verilog/System Verilog
Experience in optimization of microarchitecture and RTL for area and power reduction
Experience using ASIC design tools such as VCS, Verdi, Design Compiler, power estimation tools (Spyglass, PTPX)
Hands on experience with AXI, APB bus protocols
B.Tech/B.E/M.Tech/M.E
Nice to have8
Experience with SoC integration
Optimization of Arithmetic units, Floating point data path design
Knowledge of scripting languages (Shell, Perl, Python), C language
Experience with signing off RTL, synthesized netlist for Physical Design and eventually tape-out
Experience with PCIe, UCIe protocols
Prior domain experience in Artificial Intelligence and/or Near Memory acceleration
Experience with hardware architecture exploration, performance modeling
PPA - Power Performance, & Area analysis
Skills
Verilog
System Verilog
VCS
Verdi
Design Compiler
Spyglass
PTPX
Shell
Perl
Python
C
AXI
APB
PCIe
UCIe
Position Summary
About Samsung Semiconductor India Research (SSIR)
With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.
As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.
Role and Responsibilities
•
At least 6-10 years of experience in Low power RTL design, microarchitecture, synthesis, timing closure, power estimation. Should be proficient in Verilog/System Verilog.
•
Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with SoC integration, optimization of Arithmetic units, Floating point data path design is a plus.
•
Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler, power estimation tools(such as Spyglass, PTPX). Knowledge of scripting languages (Shell, Perl, Python), C language is a plus.
•
Experience with signing off RTL, synthesized netlist for Physical Design and eventually tape-out is desirable.
•
Hands on experience with AXI, APB bus protocols is a must. Experience with PCIe, UCIe protocols is a plus.
•
Prior domain experience in Artificial Intelligence and/or Near Memory acceleration is a plus.
•
Experience with hardware architecture exploration, performance modeling is desirable.
•
*PPA - Power Performance, & Area analysis
Skills and Qualifications
Experience – 6 to 10 Years of experience
Qualifications
•
B.Tech/B.E/M.Tech/M.E
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.