Advanced Packaging & Integration Lead
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Before you apply
LocationDublin
Work modehybrid
Typefull-time
SeniorityLead
Experience7+ yrs
DepartmentCryo-CMOS
Company size51–200 people
PostedSep 21, 2026 · 1mo ago
Verified live3h ago
At a glanceSummarised by Seekless from the posting.
Master’s or PhD in Electrical Engineering, Materials Science, Physics, Microelectronics, or a related field
7+ years’ experience in 3D integration and advanced packaging, including TSVs, fine-pitch micro-bumps, and flip-chip bonding
Experience with 3D-IC layout, planning, and simulation platforms for multi-die co-design, TSV floorplanning, and vertical interconnect planning
Experience with multi-physics analysis tools such as Ansys HFSS/Q3D or equivalent for signal/power integrity, RF analysis, and cryogenic structural/thermal stress
Experience managing technical transfers and working closely with external semiconductor advanced packaging facilities, OSATs, or research partners
Proven ability to guide technical strategy and work effectively across multidisciplinary engineering teams
Experience with cryogenic electronics, semiconductor physics, or silicon spin qubits
Knowledge of material behaviour at extreme temperatures, including superconductors and low-loss dielectrics
Experience leading or mentoring engineers in a high-tech, fast-paced R&D environment
Skills
TSVs
micro-bumps
flip-chip bonding
Ansys HFSS
Ansys Q3D
About the role
We are seeking an experienced Advanced Packaging & Integration Lead to join our team and develop packaging solutions for multi-chip silicon spin-qubit devices within a scalable quantum system.
In this role, you will work with a multidisciplinary team to drive the R&D of complex multi-chip modules utilising TSVs and micro-bumps, optimised for operation at millikelvin temperatures. You will have a significant influence on the physical architecture of next-generation quantum processors, shaping how advanced packaging subsystems integrate into the overall quantum computing solution.
Main Duties and Responsibilities
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Drive the high-level strategy and architectural design of 3D integrated circuits and multi-chip quantum modules.
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Develop advanced packaging solutions using TSVs, fine-pitch micro-bumps, and flip-chip bonding.
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Ensure packaging architectures and interconnects can withstand thermal cycling down to the millikelvin regime without delamination or loss of reliability.
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Contribute to early-stage architecture and co-design activities, ensuring the advanced packaging subsystem scales with the requirements of the overall quantum system.
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Develop simulation approaches to evaluate packaging and process options at DC and RF frequencies, including signal integrity, power integrity, thermal performance, and mechanical stress.
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Balance R&D execution with a strong focus on yield improvement, failure analysis, manufacturability, and long-term hardware reliability.
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Own relevant technical activities with external suppliers, OSATs, and research partners.
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Support the transfer of novel packaging designs into external manufacturing and advanced packaging lines.
Experience and Qualifications
Required
•
Master’s or PhD in Electrical Engineering, Materials Science, Physics, Microelectronics, or a related field.
•
7+ years’ experience in 3D integration and advanced packaging, including TSVs, fine-pitch micro-bumps, and flip-chip bonding.
•
Experience with 3D-IC layout, planning, and simulation platforms for multi-die co-design, TSV floorplanning, and vertical interconnect planning.
•
Experience with multi-physics analysis tools such as Ansys HFSS/Q3D or equivalent for signal/power integrity, RF analysis, and cryogenic structural/thermal stress.
•
Experience managing technical transfers and working closely with external semiconductor advanced packaging facilities, OSATs, or research partners.
•
Proven ability to guide technical strategy and work effectively across multidisciplinary engineering teams.
Desired
•
Experience with cryogenic electronics, semiconductor physics, or silicon spin qubits.
•
Knowledge of material behaviour at extreme temperatures, including superconductors and low-loss dielectrics.
•
Experience leading or mentoring engineers in a high-tech, fast-paced R&D environment.