Senior Analog IC Layout Engineer - MCU
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Before you apply
Salary€51k – €70k
LocationCatania
Typefull-time
SenioritySenior
Experience8–12 yrs
EquityIncluded
Company size10,000+ people
PostedOct 6, 2026 · 1mo ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
BSEE or MSEE
Approximately 8-12+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS
Expert in Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, and PVS DRC/LVS/ERC
Strong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, and DFM practices
Proven experience leading analog-on-top and digital-on-top chip layouts
Experience with floorplanning, power distribution, ESD, and multiple voltage domains
Familiarity with PLL, OSC, ADC, DAC, LDO, Bandgap, and high-speed interface circuits
Excellent communication and cross-functional leadership skills
Fluent in English
SKILL or Perl scripting is a plus
Skills
Cadence Virtuoso XL
PVS DRC/LVS/ERC
SKILL
Perl
Role Summary
The Senior Layout Engineer is a highly skilled technical contributor responsible for the physical implementation of complex analog, mixed-signal, and custom IC designs. Working with a high degree of independence, this role drives layout execution from floorplanning through tape-out, ensuring that performance, quality, reliability, and schedule objectives are achieved.
The position requires strong expertise in advanced layout methodologies, excellent problem-solving capabilities, and effective collaboration with design, verification, and technology teams. In addition to delivering critical project milestones, the engineer provides technical guidance to less experienced engineers, contributes to methodology improvements, and plays a key role in mitigating project risks and supporting successful silicon delivery.
Key Responsibilities
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Lead the layout implementation of complex analog, mixed-signal, and custom digital blocks.
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Drive floorplanning, device matching, routing strategies, and layout optimization to meet performance, area, power, reliability, and manufacturability requirements.
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Perform and review physical verification activities, including DRC, LVS, ERC, EM/IR, latch-up, density, and reliability checks.
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Collaborate closely with design, verification, technology, and product engineering teams to resolve layout-related challenges and achieve project milestones.
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Support advanced-node technologies, including FinFET processes, and contribute to methodology improvements and best practices.
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Provide technical guidance and mentorship to junior engineers and contractors.
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Assess project risks, estimate layout effort, and drive execution to meet aggressive schedules.
Expected Competencies
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Strong expertise in analog layout techniques, matching, shielding, noise isolation, ESD-aware layout, power distribution, and high-performance routing.
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Excellent understanding of semiconductor process technologies, including planar and FinFET nodes.
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Proficiency with industry-standard EDA tools and physical verification flows.
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Ability to independently make technical trade-offs and solve complex implementation issues.
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Strong communication and stakeholder management skills.
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Proven track record of successful tape-outs and delivery of high-quality silicon.
Impact and Leadership
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Recognized technical expert within the layout organization.
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Influences project execution and physical design methodologies across multiple programs.
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Contributes to organizational capability growth through mentoring, reviews, and knowledge sharing.
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Plays a key role in achieving project schedules and silicon quality targets.
Qualifications
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BSEE or MSEE.
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Approximately 8-12+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS.
•
Expert in Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, and PVS DRC/LVS/ERC.
•
Strong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, and DFM practices.
•
Proven experience leading analog-on-top and digital-on-top chip layouts.
•
Experience with floorplanning, power distribution, ESD, and multiple voltage domains.
•
Familiarity with PLL, OSC, ADC, DAC, LDO, Bandgap, and high-speed interface circuits.
•
Excellent communication and cross-functional leadership skills.
•
Fluent in English
•
SKILL or Perl scripting is a plus.
Legal
NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.
As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.
About the company
More information about NXP in Italy…