Lead DFT Engineer (Edge Computing)
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Before you apply
LocationIndia, Bangalore
Work modeon-site
Typefull-time
SeniorityLead
Experience12+ yrs
DepartmentHardware
Company size51–200 people
PostedFeb 18, 2026 · 8mo ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
12+ years in DFT
At least 2 years in a leadership or principal role
Mastery of industry-standard tools (Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus)
Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities
Deep expertise in SCAN
Deep expertise in IJTAG (IEEE 1687)
Deep expertise in boundary scan (IEEE 1149.1/6)
Proven track record with FinFET nodes (7nm, 5nm, or below)
Experience managing DFT in multi-voltage/power-gated designs
Skills
Synopsys TestMAX
Siemens/Mentor Tessent
Cadence Modus
MBIST
Boundary Scan
IJTAG IEEE 1687
SCAN
ATPG
About the company
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
About the role
Job Description: Lead DFT Engineer (Edge Computing)
Developing silicon for Edge Computing isn’t just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.
As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.
Responsibilities
Key ResponsibilitiesArchitectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.
Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.
Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.
Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.
Technical Requirements
Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role.
Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).
Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).
Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).
Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.