Design Verification Engineer - Internal IP
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Before you apply
SalaryNo pay range posted
LocationSan Jose
Work modeon-site
Typefull-time
DepartmentASIC
Company size501–1,000 people
PostedJun 11, 2025 · 1y ago
Verified live2d ago
May no longer be actively hiring
Posted by the company on Jun 11, 202556% of this company's open roles have been listed for 90+ daysNo pay range listed, though California requires one
At a glanceSummarised by Seekless from the posting.
Proficiency with UVM and SystemVerilog
Strong debugging and problem-solving skills for complex digital designs
Solid knowledge of computer architecture and digital design fundamentals
Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics
Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques
Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols
Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows
Skills
UVM
SystemVerilog
SystemVerilog Assertions (SVA)
Python
Perl
TCL
Benefits
Health insurance
Dental insurance
Vision insurance
Housing subsidy
Relocation support
Fitness benefits
Mental health benefits
Meal benefits
Unlimited compute budget
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Key responsibilities
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Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
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Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
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Debug complex datapath and protocol issues in RTL and testbench environments.
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Work closely with architects and designers to validate functionality and design intent.
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Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
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Contribute to reusable DV infrastructure, coverage models, and methodology improvements.
You may be a good fit if you have
•
Proficiency with UVM and SystemVerilog.
•
Strong debugging and problem-solving skills for complex digital designs.
•
Solid knowledge of computer architecture and digital design fundamentals.
•
Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Strong candidates may also have experience with
•
Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
•
Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
•
Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.
Benefits
•
Medical, dental, and vision packages with generous premium coverage
•
$500 per month credit for waiving medical benefits
•
Housing subsidy of $2.5k per month for those living within walking distance of the office
•
Relocation support for those moving to San Jose (Santana Row)
•
Various wellness benefits covering fitness, mental health, and more
•
Daily lunch + dinner in our office
•
Unlimited compute budget subject to ROI justification
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.