Principal Digital Design Engineer
Salary$185k – $240k
LocationSan Jose, California, United States
Typefull-time
SeniorityLead
Experience8+ yrs
DepartmentDesign Engineering CCE2
Company size1,001–5,000 people
PostedOct 5, 2026 · 1w ago
Verified live15h ago
At a glanceSummarised by Seekless from the posting.
Strong academic and technical background in electrical engineering
Bachelor's degree in EE is required
+8 years' experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage
Professional attitude with ability to prioritize dynamic tasks, plan and prepare for customer meetings, work with minimal guidance
Entrepreneurial, open-mind behavior and can-do attitude
Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet
Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
Experience with Synopsys and/or Cadence digital design tools/flows
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (≤28nm) design
Master's degree is preferred
Firmware development with C-language, scripting with Python or other equivalent programming languages
Development/support for PCIe or Ethernet Switch products
Authorized to work in the US and start immediately
Skills
PCI-Express
Ualink
Esun
Ethernet
RTL
Synopsys
Cadence
DFT
UVM
C
Python
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description
We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
Basic Qualifications:
•
Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
•
+8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
•
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
•
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
•
Authorized to work in the US and start immediately.
Required Experience:
•
Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
•
Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
•
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
•
Experience with Synopsys and/or Cadence digital design tools/flows
•
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
•
Familiarity with UVM based design verification
•
Silicon bring-up and debug expertise
•
Small-geometry CMOS (≤28nm) design
Preferred Experience:
•
Firmware development with C-language, scripting with Python or other equivalent programming languages.
•
Development/support for PCIe or Ethernet Switch products.
The base salary range is $185,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.