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Tensordyne

System Software Engineer, Networking

SalaryNo pay range posted
LocationSunnyvale
Work modeon-site
Typefull-time
SenioritySenior
DepartmentEngineering
Company size20+ people
First seenOct 5, 2026 · 6d ago
Verified live1d ago
California law requires most employers to post a pay range.
At a glanceSummarised by Seekless from the posting.
Must have8
BS or MS in Electrical Engineering, Computer Science, or a related technical field, or equivalent practical experience
Strong experience designing and operating data center or HPC networks, ideally supporting distributed AI or other tightly-coupled workloads
Deep, hands-on familiarity with the networking stack across layers — L2/L3 forwarding, ECMP, BGP, RoCE, QoS, PFC, buffer tuning, and telemetry — and comfort reasoning about how they interact end-to-end
Demonstrated willingness and ability to optimize a system by working through multiple layers: userspace services, the Linux kernel and network drivers, and firmware/SDK layers underneath
Solid software engineering fundamentals: clear interfaces, thoughtful data models, state-machine design, error handling, testing, observability, and maintainable code in C/C++, Python, Go, and/or Rust
Strong hands-on skills in network configuration, debugging, and performance tuning, and a track record of chasing hard problems across software, hardware, and vendor boundaries
Ability to independently drive ambiguous, open-ended networking work from problem definition through implementation, validation, rollout, and support
Excellent technical communication skills, with the ability to explain complex networking concepts and practical trade-offs clearly
Nice to have7
Experience with SONiC or comparable network operating system stacks (FBOSS, Cumulus Linux, or equivalent platform software), and with SAI implementations
Experience integrating or debugging switch ASIC SDKs from Broadcom, Marvell, NVIDIA, Intel, or comparable vendors
Familiarity with InfiniBand and high-performance Ethernet fabric design
Platform and board-level bring-up experience touching thermal and fan control, power monitoring, transceivers, watchdogs, CPLDs, OSFP/CMIS, or LEDs
Experience with OpenConfig gNMI, YANG data models, or other structured telemetry
Comfort with CI/CD pipelines, reproducible builds, distributed config and state management, and large-scale automation
Prior technical leadership or mentoring experience
Eligibility1
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations
Skills
C/C++
Python
Go
Rust
SONiC
SAI
InfiniBand
OpenConfig gNMI
YANG
CI/CD
BGP
RoCE
ECMP
PFC
ECN
DCQCN
Benefits
Health insurance
Flexible spending
System Software Engineer, Networking
About Tensordyne
AI is reshaping our world, taking on cognitive work that once belonged only to humans — perceiving across modalities and environments, learning quickly, and solving hard problems. Tensordyne is an AI systems company building very high-performance, low-power generative AI inference platforms. Through custom silicon, hardware, and software, our mission is to accelerate multimodal generative AI inference at scale with safe, sustainable, high-performance systems for our hyperscaler and neocloud data center customers.
We are a well-funded, fast-paced startup with headquarters in Sunnyvale, CA and Munich, Germany, plus talented team members working remotely across North America and Europe. We take care of our people and their families with comprehensive benefits, competitive compensation, flexible spending options, and recognition programs — because category-defining technology starts with a healthy, supported team. Come help us shape the future of multimodal generative AI.
About the Role
We are looking for a Networking Engineer to design, build, and optimize the multi-hop fabrics that connect Tensordyne’s AI inference systems at rack, pod, and cluster scale. This is a deeply technical, hands-on role for someone who is at home moving up and down the stack — tuning userspace services, patching kernel drivers, and reaching into firmware — to squeeze latency, bandwidth, and reliability out of large, lossless networks.
You will own networking problems end-to-end: from topology and fabric architecture through control-plane behavior, data-plane programming, and the hardware and firmware that sit underneath. The ideal candidate treats “the network” as one continuous system spanning application, operating system, ASIC, and optics, and is energized by chasing a single packet path across all of those boundaries.
This role is based on-site at our Sunnyvale, CA headquarters.
What You’ll Do
•
Architect ultra-high-bandwidth, non-blocking multi-hop scale-out fabrics (Clos spine–leaf and super-spine style topologies) for large-scale distributed AI inference, and define redundancy, oversubscription, and performance targets.
•
Optimize lossless Ethernet and RDMA/RoCE transport using congestion-control mechanisms such as PFC, ECN, and DCQCN, including buffer and QoS tuning tied to real workload behavior.
•
Work across the full stack — userspace control-plane services, the Linux kernel and network device drivers, switch ASIC SDK/SAI layers, and platform firmware — to diagnose and remove bottlenecks wherever they live.
•
Drive route, neighbor, next-hop, and ECMP programming flows from control-plane intent all the way to confirmed ASIC hardware state, and build mechanisms that distinguish control-plane acceptance from SDK acceptance from hardware programming acknowledgement.
•
Select and validate switches, optics, transceivers, and cabling systems, and lead fabric bring-up, link training, SerDes tuning, and performance baselining together with hardware and platform teams.
•
Build and maintain high-resolution telemetry pipelines that surface network health, detect microbursts, and expose congestion patterns across the fleet.
•
Develop automation for provisioning, configuration management, and remediation, and contribute to reproducible build and rollout pipelines for network software and images.
•
Debug complex, cross-boundary issues that span kernel drivers, platform monitoring, routing and control-plane agents, ASIC state, optics, firmware, and topology.
•
Define deployment standards and operational best practices so fabrics can be stood up consistently across sites, and support the path from factory qualification through mass deployment.
•
Partner closely with silicon, hardware, platform, and manufacturing teams, and help evaluate next-generation networking technologies and vendor solutions.
•
Mentor teammates and help shape Tensordyne’s long-term networking strategy and roadmap.
What We’re Looking For
•
Strong experience designing and operating data center or HPC networks, ideally supporting distributed AI or other tightly-coupled workloads.
•
Deep, hands-on familiarity with the networking stack across layers — L2/L3 forwarding, ECMP, BGP, RoCE, QoS, PFC, buffer tuning, and telemetry — and comfort reasoning about how they interact end-to-end.
•
Demonstrated willingness and ability to optimize a system by working through multiple layers: userspace services, the Linux kernel and network drivers, and firmware/SDK layers underneath.
•
Solid software engineering fundamentals: clear interfaces, thoughtful data models, state-machine design, error handling, testing, observability, and maintainable code in C/C++, Python, Go, and/or Rust.
•
Strong hands-on skills in network configuration, debugging, and performance tuning, and a track record of chasing hard problems across software, hardware, and vendor boundaries.
•
Ability to independently drive ambiguous, open-ended networking work from problem definition through implementation, validation, rollout, and support.
•
Excellent technical communication skills, with the ability to explain complex networking concepts and practical trade-offs clearly.
•
BS or MS in Electrical Engineering, Computer Science, or a related technical field, or equivalent practical experience.
Nice to Have
•
Experience with SONiC or comparable network operating system stacks (FBOSS, Cumulus Linux, or equivalent platform software), and with SAI implementations.
•
Experience integrating or debugging switch ASIC SDKs from Broadcom, Marvell, NVIDIA, Intel, or comparable vendors.
•
Familiarity with InfiniBand and high-performance Ethernet fabric design.
•
Platform and board-level bring-up experience touching thermal and fan control, power monitoring, transceivers, watchdogs, CPLDs, OSFP/CMIS, or LEDs.
•
Experience with OpenConfig gNMI, YANG data models, or other structured telemetry.
•
Comfort with CI/CD pipelines, reproducible builds, distributed config and state management, and large-scale automation.
•
Prior technical leadership or mentoring experience.
Tensordyne’s culture was built on the following values
•
Put people first. We only succeed when our people succeed.
•
Ethics and integrity always; Being open, honest, and respectful of everyone.
•
Think Big. Be ambitious and have audacious goals.
•
Aim for excellence. Quality and excellence count in everything we do.
•
Own it and get it done. Results matter!
•
Make each person better together, than they would be as an individual.
•
Embrace each others’ differences, and embrace that there will be differences.
Additional Information
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.
More roles at Tensordyne
Senior ASIC Physical Design EngineerForward Deployed Inference EngineerSystems Performance Modeling EngineerSenior Enterprise Sales Executive – AI Inference InfrastructureSr. Staff ASIC Design Engineer
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