Senior Principal Engineer
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Before you apply
LocationNoida
Typefull-time
SeniorityLead
Company size10,000+ people
PostedOct 12, 2026 · 3w ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
Hands-on experience in Scan insertion, ATPG, GLS
Responsible for understanding the DFT architecture of the design and providing scan insertion collaterals to implementation team
Proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test
Contribute to ATPG at partition and SoC level
Experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis
Familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG)
Effective communication and teamwork skills, with the ability to collaborate across functions
Skills
Mentor Tessent
Synopsys DFT Compiler
Cadence Encounter Test
DFT GLS simulation tools
IEEE 1149.1 (JTAG)
IEEE 1687 (IJTAG)
Job Description
Responsibilities
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. And will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis.
Requirements
Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. .
Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
Effective communication and teamwork skills, with the ability to collaborate across functions.