Yield Diagnostics Engineer, up to staff
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Before you apply
LocationHsinchu City, Taiwan
Work modeon-site
Typefull-time
SeniorityLead
Experience5+ yrs
DepartmentASICS Engineering
Company size10,000+ people
First seenOct 30, 2026 · 5d ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
M.S. or Ph.D. in Electrical Engineering or a related field, with 5+ years of relevant industry experience
Strong experience in yield analytics, diagnostics, and semiconductor data analysis
Proven track record of driving yield improvement in high-volume manufacturing environments
Solid understanding of Digital design architecture, DFT methodologies (scan, ATPG, etc.), and Test flows including ATE and SLT
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience OR Master's degree in Science, Engineering, or related field and 3+ years of experience OR PhD in Science, Engineering, or related field and 2+ years of experience
Strong knowledge of high-voltage devices (e.g., LDMOS) and ability to interpret device characteristics
Experience with semiconductor process integration and hands-on experience supporting yield ramp in high-volume manufacturing
Deep expertise in scan diagnosis techniques and tools for volume yield analysis
Hands-on experience applying ML/AI techniques in yield analytics and diagnostics
Skills
scan
ATPG
ATE
SLT
machine learning
AI
Company:
Qualcomm Semiconductor Limited
Job Area:
About the role
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
We are seeking a highly driven engineer to lead yield analysis & diagnostics across digital and high-voltage product lines. This role emphasizes data-driven yield improvement, scalable diagnostics, and automation, enabling faster root cause resolution and robust high-volume manufacturing. The ideal candidate will bring strong technical depth, agility, and a mindset focused on building repeatable, efficient yield engineering solutions. You will work cross-functionally with foundry, test, product, and quality teams to systematically identify yield limiters and drive sustainable improvement across the product lifecycle.
Responsibilities
Key Responsibilities:
•
Drive end-to-end yield analysis across wafer sort, final test, and system-level screening
•
Identify yield detractors through statistical data mining, failure signature analysis, and silicon correlation
•
Lead cross-functional root cause analysis (RCA) and corrective actions with foundry, test, and process integration teams
•
Develop and scale yield monitoring frameworks, KPIs, and automated dashboards
•
Drive automation and methodology improvements to increase engineering efficiency and scalability
Requirements
Qualifications:
•
M.S. or Ph.D. in Electrical Engineering or a related field, with 5+ years of relevant industry experience.
•
Strong experience in yield analytics, diagnostics, and semiconductor data analysis.
•
Proven track record of driving yield improvement in high-volume manufacturing environments.
•
Solid understanding of Digital design architecture, DFT methodologies (scan, ATPG, etc.), and Test flows including ATE and SLT
Nice to have
Preferred Qualifications:
•
Strong knowledge of high-voltage devices (e.g., LDMOS) and ability to interpret device characteristics
•
Experience with semiconductor process integration and hands-on experience supporting yield ramp in high-volume manufacturing
•
Deep expertise in scan diagnosis techniques and tools for volume yield analysis
•
Hands-on experience applying ML/AI techniques in yield analytics and diagnostics
Minimum Qualifications:
• Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Legal
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