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Samsung Electronics

Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology

Salary$180k – $270k
Location3900 N Capital of Texas Hwy, Austin, TX, USA
Work modeon-site
Typefull-time
SeniorityLead
Experience11+ yrs
DepartmentEngineering
Company size10,000+ people
PostedJul 31, 2026 · 2mo ago
Verified live13h ago
At a glanceSummarised by Seekless from the posting.
Must have9
15+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 13+ years with a Master's Degree, or 11+ years with a Ph.D.
10+ years of custom design tools and methodology development experience
10+ years of experience with industry standard automated design tools for synthesis, place and route, EM/IR analysis, static timing analysis and/or physical verification
10+ years of experience working with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows
Experience with PPA analysis across standard cell library, memory compiler, interconnect stack options and block-level PPA evaluation
Strong knowledge of CMOS fundamentals, device physics, device-technology interactions, scaling trends, and design and implementation challenges at advanced technology nodes
Experience working with batch run oriented environments for design space exploration and high throughput
Strong skills with scripting/programming languages like Tcl, Perl, Python
Strong data analysis skills to analyze and deduce information from large data sets and apply the learnings to other scenarios
Nice to have2
Experience working with foundries
Experience in improving productivity, efficiency and/or quality of results through machine-learning practices
Eligibility1
U.S. export control - must be authorized to access controlled information or eligible for government authorization
Skills
Cadence Innovus
Synopsys Fusion Compiler
Tcl
Perl
Python
machine-learning
Benefits
Health insurance
Dental insurance
Vision insurance
Life insurance
401(k)
Free onsite lunch
Employee purchase program
Tuition assistance
Paid time off
Student loan program
Wellness incentives
Position Summary
About the company
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role and Responsibilities
You will join our growing Global Advanced Technology Enablement team that is specialized in driving technology development across Samsung System LSI business. We engage with Foundry partners from the very early phase to thoroughly explore target technology for next-generation SoC products.
As a highly experienced DTCO engineer, you will help propel Samsung SARC/ACL’s innovation forward by building highly efficient design and analysis flows and methodologies for DTCO. With strong expertise in digital design flows spanning synthesis, PnR, EM/IR, STA, PV and large-design space exploration, you will drive collaboration with the IP development teams to ensure process technology, design rule, standard cell design and design methodology changes are consumable throughout the product development cycle to meet or exceed product key performance indicators.
•
You are an innovator. You are skilled at developing CAD flows for custom design with a mindset to continuously push the PPA (power/performance/area) envelope on aggressive designs with a high level of automation for DTCO needs.
•
You have a curious mindset and thrive on navigating the unknown through innovation and continuous learning. You will explore a methodology to achieve low-power and high-performance goals for Samsung-specific SOC design styles.
•
You have expertise in one or many technical areas, including concepts of logic/physical synthesis, automated place and route, power estimation, and standard cell design.
•
You are a problem solver. You enjoy solving CAD and design methodology-related challenges and creating analysis methodologies and metrics most relevant to removing bottlenecks for improvement.
•
You thrive in a production and result-oriented environment, working on high-impact, large-scale projects that have a global impact.
•
You are skilled at working effectively with various stakeholders by using clear and precise communication skills for technical requirements and specifications, while proactively driving collaboration with cross-functional teams.
•
You are detail oriented. You can provide and maintain thorough documentation, publish results, and fulfill other project management-related needs.
•
You are a self-starter and driver. You enjoy seeking new problems and owning solutions to drive toward production.
Skills and Qualifications
•
15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D.
•
10+ years of custom design tools and methodology development experience.
•
10+ years of experience with industry standard automated design tools for synthesis, place and route, EM/IR analysis, static timing analysis and/or physical verification.
•
10+ years of experience working with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows.
•
Experience with PPA analysis across standard cell library, memory compiler, interconnect stack options and block-level PPA evaluation.
•
Strong knowledge of CMOS fundamentals, device physics, device-technology interactions, scaling trends, and design and implementation challenges at advanced technology nodes.
•
Experience working with batch run oriented environments for design space exploration and high throughput.
•
Experience working with foundries is a plus.
•
Experience in improving productivity, efficiency and/or quality of results through machine-learning (ML) practices is preferred.
•
Strong skills with scripting/programming languages like Tcl, Perl, Python.
•
Strong data analysis skills to analyze and deduce information from large data sets and apply the learnings to other scenarios.
Our Team
Samsung System LSI values the strategic importance of DTCO/TE activities, especially for advanced technology beyond 5nm nodes. Our goal is to maximize Samsung LSI’s product benefits, often measured by PPA, Silicon Reliability, and design TAT. You will join us in driving Foundry/EDA/Foundation IP (FIP)-Development to unlock new technology potential, which is key towards our business success.
Here you are part of a diverse global task force with a cross-functional scope, focusing on collaboration and growth to scale quickly with the financial backing of a company leading globally in innovation. Being part of a unique growing team means you have limitless room to explore, innovate, and grow by wearing different hats. You will experience multiple aspects of the development cycle and see your work in an end-user product. Learning always happens and you are encouraged to think outside the box to turn ideas into reality.
Total Rewards
At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $270,400. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.
Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees are eligible for MBO bonus compensation, based on company, division, and individual performance. Additionally, this role might be eligible to participate in long term incentive plan and relocation.
Trade Secrets
By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.
U.S. Export Control
This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.
#SARC
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* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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