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Astera Labs

Manager, Digital Design

Salary$216k – $240k
LocationSan Jose, California, United States
Work modeon-site
Typefull-time
DepartmentSilicon Engineering CCE1
Company size1,001–5,000 people
First seen3d ago
Last seen1d ago
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.
This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems.
Key Responsibilities
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End-to-End Chip Development
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Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.
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Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
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Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations.
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RTL Quality and Tape-Out Readiness
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Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out.
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Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.
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Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.
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Team and Cross-Functional Leadership
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Lead, mentor, and develop a team of 6–8 digital design engineers, fostering technical excellence, accountability, and effective collaboration.
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Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution.
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Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership.
Basic Qualifications
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Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
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Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
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3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
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Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity.
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Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
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Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.
Preferred Qualifications
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Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
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Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes.
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Building design blocks with large physical floorplan sizes is a plus
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Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.
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Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
Benefits
Salary range is $216,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
Legal
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
More roles at Astera Labs
Tech Lead PCB Layout EngineerTemplate JobSenior System Validation EngineerLead Logic Design - PCIE IP/Subsystem EngineerPrincipal Logic Design Engineer - UALink IP/Subsystem
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