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Role Overview:
The DV Architect is a senior technical leadership role responsible for the strategic vision and infrastructure of verification for next-generation Tensilica advanced CPU cores and configurable processors. You will define the methodologies that ensure the functional integrity of highly complex instruction set architectures (ISA).
Key Responsibilities:
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Methodology Strategy: Define and own the long-term DV architecture, focusing on scalability across multiple processor variants and generations.
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Verification Infrastructure: Architect simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
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Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis.
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Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.
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Mentorship: Provide technical direction and set the standard for quality and metric-driven verification (MDV) across global teams.
Required Qualifications:
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B.Tech/M.Tech in ECE with 4 to 8 years of experience in SoC/CPU/DSP verification.
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Deep expertise in SystemVerilog/UVM and C/C++ for architectural modeling.
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Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
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Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
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Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.
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