Cadence

EntryPythonShellPerlLinux

Configuration Management Engineer II

Mid2+ yrsPythonUnixLinuxLLM

Product Engineer II, Conformal

2 Locationsfull-time$105k – $195k4d ago

Mid3+ yrstclperlRTL Synthesisverification tools

Internship Position (Digital Signoff Group)

AI for Smarter IP Design Workflows

EntryC++C++17LinuxUnix

VALBONNE (Sophia)on-siteinternship4d ago

Python

Senior5+ yrsPerlTclshell scripting

Staff Systems Engineer (Infrastructure Automation & Virtualization)

Senior5–8 yrsPythonTerraformAnsibleNutanix AHV

Lead Software Engineer - Low Power Verification

SAN JOSEon-sitefull-time$115k – $213k4d ago

Senior2+ yrsIEEE 1801 UPFVerilogSystemVerilogVHDL

PerlTclshell scriptingVerilog

Mid4–7 yrsVerilogSystemVerilogVHDLRTL design

Product Engineer II

SAN JOSEfull-time$105k – $195k4d ago

MidUp to 4 yrsSPICEFastSPICEPythonPerl

Principal Product Engineer – High-Speed IP SerDes

Senior5+ yrsRTLgate-level simulationsynthesisSTA

Principal Product Engineer – High-Speed IP UCIE

Senior5+ yrsRTLgate-level simulationsynthesisSTA

Design Engineer II

Nanjingon-sitefull-time4d ago

Senior1+ yrsRTLSystem VerilogPythonC/C++

Software Engineer II: Hardware Verification Compiler

BELO HORIZONTEon-sitefull-time4d ago

Mid3+ yrsCC++System VerilogUnix

Sr Principal Infrastructure Software Engineer

SAN JOSEon-sitefull-time$161k – $299k4d ago

Senior7–10 yrsJavaPerlJavaScriptTypeScript

Senior15+ yrsSynthesisPhysical implementationTiming closureSignoff

Sr. Principal Product Engineer

SAN JOSEon-sitefull-time$161k – $299k4d ago

Senior6–10 yrsVoltusIntegrityTempusInnovus

Senior5+ yrsVerilogHVLSVe

Mid5+ yrs

Senior3–6 yrsCC++VerilogSystemVerilog

Sr Principal Product Validation Engineer

SeniorVerilogVHDLEDACadence

HYDERABAD 04full-time4d ago

Mid4–7 yrsCadencePythonSKILLPerl

HELSINKI 03full-time4d ago

Senior5+ yrsCC++SpectreHSpice

PUNEon-sitefull-time4d ago

Senior8–10 yrsVerilogSystemVerilogPerlUnix shell

4 Locationsfull-time4d ago

MidVerilogSystemVerilogUVMAXI3

Design engineering Architect

HYDERABADon-sitefull-time4d ago

Senior15–25 yrsCadenceMentor GraphicsSynopsysSRAM

Sr Design Engineering Architect

Senior6–16 yrsRTLVerilogSystemVerilogUVM

Senior7–12 yrsRTLDFTscan insertionLEC

Design Engineering Manager

Manager4–10 yrsPost-Silicon Physical Layer Electrical ValidationPCIeUSBDP

Mid6–10 yrsVerilogSystem VerilogUVMLint

Lead Hardware Engineer - DFT IP R&D

Senior4–6 yrsVerilogSystemVerilogUVMPerl

webcloudservice-oriented technologieslibrary management

NOIDA 02on-sitefull-time4d ago

Senior4–6 yrsC++Python

Lead Product Engineer - MIPI Protocol

Senior7–12 yrsMIPICSI2DSII3C

SeniorTclPythonshell scriptingCadence Liberate

Sr Principal Application Engineer

Senior12+ yrsFPGAProtium X3SystemVerilogVHDL

CORK 01on-sitefull-time4d ago

Senior4+ yrsCMOSSERDESDDRPLL

Senior7–12 yrsIR/EM analysis tools

Lead Software Engineer for Virtuoso ADE

C++Cloud computingmachine learningAPIs

SeniorVerilogSystemVerilogPCIeAXI

Intern

EntryVerilogTclPerlshell scripting

SeniorARMRISC-VPCIePerspec

3 Locationson-sitefull-time4d ago

Senior4+ yrsVerilogSystemVerilogUVMPython

SeniorRTL codingLINTSDCCDC

Senior4+ yrsSystemVerilogUVMSV

Senior9+ yrsASICfloor planningpower grid designplace and route

Senior12+ yrsSystemVerilogUVMCC++

Functional Verification Engineer - Applied ML

PETAH TIKVAon-sitefull-time4d ago

MidFormalSV/UVMOVMVerilog

Lead Software Engineer (Back-End Engineer)

MidC/C++LinuxAI/MLEDA

Senior5+ yrsPythonpytestDjangoGoLang

Senior12+ yrsvManagerSystemVerilogVHDLC/C++

MidTempusPrimeTimeSTATcl

Senior15 yrsPythonLLMRAGLLMs

Sr. Principal Product Engineer – Digital & Signoff Group (DSG)

Senior6–8 yrsTclPythonPerl

Sr. Principal Software Engineer

AUSTINfull-time$196k – $364k4d ago

SeniorVerilogSystemVerilogPerlPython

Lead Software Engineer - Compiler/LLVM

AE Director Emulation and Prototyping

Senior4+ yrsCC++LLVMGCC

SAN JOSEfull-time$158k – $293k4d ago

Senior15+ yrsPalladiumProtiumEmulationFPGA Prototyping

Sales — 6 roles

Sr. Interface IC, IP Sales Executive II

2 Locationsfull-time$248k – $372k4d ago

Mid5+ yrsSemiconductor IPMemory Interface IPProtocol IPConnectivity IP

Lead Product Engineer - Verification

Senior6+ yrsSOC EmulationAccelerationHybrid solutionUVM

Senior6+ yrsUVMVerification IPsTransactorsSimulator

Mid3+ yrsUVMVerification IPsTransactorsSimulator

Senior10+ yrsUVMVerification IPsTransactorsSimulator

Scientific Sales Executive

HOME CAremotefull-time4d ago

Mid5+ yrsSalesForce

R&D — 3 roles

SAN JOSEfull-time$115k – $213k4d ago

CC++LinuxTcl

Sr. Principal Software Engineer

Senior15+ yrsC++SKILLPythonQt

Principal EDA Software Engineer (C++, Characterization)

SAN JOSEon-sitefull-time$137k – $254k4d ago

Senior8+ yrsC++LinuxUnixSPICE

Finance — 2 roles

Sr Sales Finance Analyst

2 Locationshybridfull-time4d ago

SeniorSAPSalesforceCPQJIRA

Credit & Collections Specialist

DUBLINon-sitefull-time4d ago

Mid5+ yrsExcelSalesforceSAPHigh-Radius

IT — 2 roles

IT- Staff Systems Engineer (SFDC Dev 1)

Senior8+ yrsSalesforceAPEXVisualforceLWC

IT - Sr Systems Engineer (SFDC Business Systems Analyst)

Mid5+ yrsSalesforceSalesforce Sales CloudSalesforce Service CloudSalesforce Experience Cloud

Marketing — 2 roles

Intern - Digital Marketing

BRUSSELS 01on-siteinternship4d ago

EntryMarketoCRM

Tensilica Platform Marketing

SAN JOSEon-sitefull-time$203k – $377k4d ago

Lead15+ yrsARMXtensaRISC-VC/C++

AI Engineering / Quality Assurance — 1 role

Senior7+ yrsPythonBashTypeScriptGo

Analog and Mixed signal design — 1 role

Senior8+ yrsCMOSSERDESPLLCAD

Channel Strategy & Programs Office — 1 role

Revenue Intelligence Analyst

5 Locationsfull-time$95k – $176k4d ago

Senior5+ yrsExcelSQLCRMBI

Custom Products Group — 1 role

Intern Position (Custom IC Product Group)

Lead Education Application Engineer (RF/Microwave)

Entry

Customer Education — 1 role

4–6 yrsCadence VirtuosoSpectre Circuit simulatorCadence Microwave Office (AWR)Cadence EMX/EMXDesigner

GCS — 1 role

Lead Application Engineer - GCS ( Physical Design )

Lead4+ yrsPhysical design toolsSign-off toolsDigital & sign-off tool set

Information Security — 1 role

IT- Staff Software Security Engineer

Senior10–15 yrsWAFCDNPerforceGithub

IP Group — 1 role

Senior10+ yrsUVMPCIeCCIXCXL

IPG — 1 role

Intern - IC Design

GALWAY 01on-siteinternship4d ago

SpectreVirtuoso

Research & Development — 1 role

Sr. Principal Software Engineer, Physical Verification

SAN JOSEfull-time$161k – $299k4d ago

Senior10+ yrsCC++

Silicon Solutions Group — 1 role

Corkon-sitefull-time4d ago

Senior10+ yrsVerilogRTL DesignMetric Driven Verification (MDV)LINT

System Design and Analysis (SDA) — 1 role

Lead Application Engineer

FELDKIRCHEN (Munich)hybridfull-time4d ago

MidAllegro X Advanced Package Designer (APD)Sigrity

VEM team — 1 role

Senior15+ yrsC++SKILLAI programming platform

Virtual Protocols Product Engineering — 1 role

Principal Product Engineer - Virtual Protocols

SAN JOSEon-sitefull-time$137k – $254k4d ago

Senior5–7 yrsPCIECXLEthernetUSB

Other — 213 roles

Processor Core Logic Design/Architect

3+ yrs

Security Receptionist

Intern Digital Implementation

VELIZY (Paris)on-siteinternship4d ago

EntryPythonTclInnoStackCadence tools

Product Engineering Architect - Verification

Senior20+ yrsSOC Emulation/AccelerationHybrid solutionUVMVerification IPs

Intern SSG

Incisive simulatorPalladium emulator

AI Engineer, Ontologies & Knowledge Graphs

PythonREST APIsETLELT

Burlington, MAon-sitefull-time$102k – $189k4d ago

Mid2+ yrsCC++gdbLinux

Intern - CPG

Burlington, MAon-sitefull-time$102k – $189k4d ago

EntryLinuxUnixCC++

lead software engineer

2+ yrsC/C++C++gdbLinux

Design Verification Architect / Director

2 Locationson-sitefull-time$186k – $345k4d ago

Director17+ yrsSystem VerilogUVMPerlUnix shell

AI Intern - Technical Communications (System Design Analysis Group)

EntryPythonVisual StudioVS CodeGit

Product Engineering Architect

AUSTIN4d ago

Lead Verification Engineer

Senior6–10 yrsSystemVerilogUVMRTL VerificationFunctional Coverage

Lead Design Engineer ( Synthesis/LEC/CLP )

Lead5–8 yrsCadence GenusConformal LECCLPUPF

Lead Software Engineer - Low-Power Verification

SAN JOSEfull-time$115k – $213k4d ago

Senior1–4 yrsC++PerlTcl/TkPython

Principal Design Engineer - ( Synthesis/LEC/CLP )

Senior8–12 yrsSynthesisGenusLECConformal

BANGALORE 05on-sitefull-time4d ago

MidPerlTclVerilogSystem Verilog

Software Engineer II

Intern-Product Validation

CC++

SHANGHAIpart-time4d ago

UnixviTCLTK

Principal Product Engineer – High-Speed IP Memory

Senior7+ yrsRTLSynthesisSTATiming closure

Nanjingon-sitefull-time4d ago

Design Engineer II

Mid1+ yrsSystem VerilogPythonCC++

Lead Technical Communications Engineer

documentation generation agentAI agentsconfigurable documentation workflows

Senior Systems Engineer (HPC/Server Farm)

SAN JOSEon-sitefull-time$144k – $267k4d ago

Senior7+ yrsLSFSlurmIaCAzure

Nanjingon-sitefull-time4d ago

Senior5+ yrsSystem VerilogPythonC/C++Cadence ASIC design tools

Product Engineering Architect

Senior14+ yrsModus PEDFTATPGInnovus

SAN JOSEfull-time$186k – $254k4d ago

2 Locationson-site4d ago

Software Engineer

Senior3+ yrsC++UnixStatic Timing AnalysisStatistical Static Timing Analysis

Design Engineer

AUSTINfull-time4d ago

2+ yrsUVMSystem VerilogSVAAMBA

Software Engineer

AUSTINfull-time4d ago

Mid3+ yrsCC++PythonTcl

SAN JOSEhybridfull-time$220k – $254k4d ago

Senior4+ yrsC++PythonEDAVLSI

Design Engineer

Mid1+ yrsUVMSystem VerilogSVAAMBA

Application Engineer, Customer Engagement

Mid3+ yrsTCLPerlPythonEDA tools

Software Engineer

SAN JOSEhybridfull-time$153k – $213k4d ago

C++PythonSTLsort

Design Engineer

SAN JOSEhybridfull-time$115k – $189k4d ago

MidCadenceVLSIASICStatic Timing Analysis

Computer and Information Systems (Finance Systems Transformation) Manager

SAN JOSEon-sitefull-time$239k – $259k4d ago

Senior4+ yrsPythonRSQLTableau

Sr. Principal Product Engineer

SAN JOSEfull-time$239k – $286k4d ago

Senior8+ yrsCadence InnovusSynopsys IC CompilerTCLPython

Lead FrontEnd Methodology Engineer

SHANGHAIon-site4d ago

BANGALOREhybridfull-time4d ago

Senior7+ yrsPerlPythonmakeSCons

4+ yrsSigrityTCLPerlShell

Entry1+ yrsSPICEfast-spice

Lead Application Engineer

SHENZHENon-sitefull-time4d ago

Senior2–8 yrsVerilogVHDLSystem VerilogHDL simulators

Product Validation Engineer II

Mid5–10 yrsUVMC++CSVA

Sr Principal Customer Engagement Engineer - HSV

PythonPerlTclCSH

Lead Product Engineer - UCIe & Functional Verification

3 Locationson-sitefull-time4d ago

Senior5–8 yrsSystem VerilogUVMUCIe

VerilogVHDLSystemVerilogC++

Lead3–6 yrsVerilogVHDLSystemVerilogC++

Senior7+ yrsSerdesDDRHBMTx

Principal DFT Design Engineer

Senior7+ yrsDFTEDA Toolslogic simulatorsATPG

Senior4+ yrsSVUVMSystem Verilog

Intern-Product validation engineer

SHANGHAIinternship4d ago

EntrySigrityClarity

Product validation engineer Intern

SHANGHAIinternship4d ago

EntrySigrityClarity

Senior DFT Engineer

Senior5–15 yrsDFTscan chain insertioncompression scanMBIST

Lead Solutions Engineer - AE

3 Locationsfull-time4d ago

5+ yrsCC++SystemC

Lead Solutions Engineer

System VerilogUVMVerilogVHDL

Senior3–6 yrsVerilogVHDLSystemVerilogC++

Lead Product Engineer - Design Verification (MM/VIP)

Lead4–8 yrsSystem VerilogUVMMemory protocolsDFI protocol

NOIDA4d ago

EDAC++SVMIPI

Senior6–10 yrsC++HDLPCIeCXL

Principal Solutions Engineer - AE

UVMPCIeCCIXCXL

Senior8+ yrsCC++SystemCscripting languages

PUNE4d ago

3+ yrsPCIeONFIXSPISD

Senior7+ yrsDDR4DDR5LPDDR4LPDDR5

Principal Product Validation Engineer

VerilogVHDLSystemVerilogC++

Design Engineering Architect

UVMPCIeCCIXCXL

Senior6+ yrsFinfet3nm/5nm7nmcustom layout

Mid4–6 yrsCShellPerlPython

Senior8+ yrsSystemVerilogUVMSVDDR

IP Sr Sales Representative

Internship Opportunities 2026

Senior5+ yrs

DUBLIN 034d ago

3+ yrsGenusInnovusTempusVoltus

PUNE4d ago

Design Engineer II

Mid2–4 yrsPCIeUSBDisplayPortEthernet

PUNEon-sitefull-time4d ago

Senior8+ yrsC++SystemCTLMPython

Lead C++ Software Engineer

SAN JOSEfull-time$111k – $205k4d ago

Senior4+ yrsCC++VerilogSystemVerilog

Lead Support Application Engineer - GCS

Mid3–7 yrsVoltusCadenceGenusInnovus

Senior11+ yrsVerilogSystemVerilogUVMAXI

Senior8+ yrsC++gdbdata structuresalgorithms

Senior3–6 yrsVerilogVHDLSystemVerilogC++

Senior3+ yrsLangchainSparkPythonC++

Senior5–12 yrsC++JavaPythonIP-XACT

Software engineer II

INVECAS HYDERABADfull-time4d ago

3–6 yrsEmbedded SoftwareDevice DriversBSPRTOS

Mid3+ yrsLangchainSparkPythonC++

BANGALORE 05on-sitefull-time4d ago

DFTATPGInnovus

Lead software enginner for LLM-infra

5+ yrsLangchainNIMSparkPython

Senior5+ yrsC++SystemCTLMPython

NEWCASTLE 01on-sitefull-time4d ago

Lead4+ yrsC++C++14C++17QT

Software Architect

Mid4+ yrsCC++VerilogSystemVerilog

Senior5+ yrsCC++

Lead4–8 yrsSystem VerilogUVMDDRHBM

Senior12–14 yrsVerilogSystemVerilogSpecman eUVM

Senior8+ yrsSystem VerilogUVMPerlUnix shell

Sr Principal Product Validation Engineer

BEIJINGfull-time4d ago

Senior6+ yrsCadence Virtuoso Design EnvironmentSPICE

Leader software engineer for jedai LLM-infra

Mid3+ yrsLangchainNIMSparkPython

Senior12–14 yrsVerilogHVLSystemVerilogSpecman e

Software Engineer II

Mid3+ yrsLLMMLbig dataLangchain

Principal Application Engineer

Senior3+ yrsASIC design flowP&RDFTEM/IR-Drop/crosstalk analysis

Principal Software Engineer-Mesh

Senior3+ yrsC++ACIS

Senior3+ yrsSOC EmulationAccelerationHybrid solutionUVM

Senior10+ yrsSimulator (IES, VCS, etc)emulator/accelerators (PXP, Zebu, Veloce)Linuxtcl

BEIJING4d ago

RTLGDS

lead software engineer

Mid3+ yrsCC++LinuxFPGA

Solutions Architect - AE

Intern-Product Validation

RTLGDSIIScriptingML

SHANGHAIon-sitepart-time4d ago

EntryUnixviTCLTK

Mid3+ yrsLinuxtclVerificationPrototyping

Senior12–14 yrsVerilogSystemVerilogSpecman eUVM

Senior Meshing Developer

Lead Product Engineer - Verification

Senior7+ yrsC++ACIS

Senior6+ yrsSOC EmulationAccelerationHybrid solutionUVM

Lead Product Engineer - Verification

Mid6+ yrsUVMVerification IPsTransactorsSimulator

Senior8–12 yrsLiberateSpectreNLDMCCS

Sr Principal Product Engineer - Verification

CShellPerlPython

GYEONGGI-DO (Seoul)4d ago

Senior15+ yrsSOC Emulation/AccelerationUVMVerification IPsTransactors

ML/AI Software Engineer

software engineering intern

BEIJINGon-siteinternship4d ago

CC++pythonpytorch

Senior10+ yrsSOC EmulationAccelerationHybrid solutionUVM

Software Engineer for SPICE (math)

BEIJING4d ago

PythonC++LinuxUnix

Senior7+ yrsSystemVerilogUVMDDRHBM

PUNE 04full-time4d ago

Intern of the Device Modeling

BEIJING 04on-site4d ago

C/C++PythonVerilog-A

Software Engineer II

BEIJING 044d ago

PythonC++PyTorchTensorFlow

Intern SSG

EntryIncisive simulatorPalladium emulator

Principal Customer Engagement Engineer

SHANGHAIon-site4d ago

RC TechfileEMIR TechfilePR TechLEFDTCO

Frontend Engineer

Mid3+ yrsRTLGDSIIlogic equivalence checkinglogic synthesis

Senior7+ yrsSystem VerilogPythonCC++

BEIJING 04on-sitefull-time4d ago

CC++

Associate Compliance Analyst II

Burlington, MAfull-time$118k – $218k4d ago

Senior3+ yrsCC++data structuresalgorithms

Application Engineer

YOKOHAMAon-sitefull-time4d ago

EDA toolsCADsemiconductor design

Application Engineer - digital implementation

YOKOHAMAon-sitefull-time4d ago

shellPerlTclPython

HRIS Architect

Lead10+ yrsWorkday HCMWorkday AbsenceWorkday Time TrackingWorkday Compensation

Sr. Principal Software Engineer

SAN JOSEfull-time$154k – $286k4d ago

CC++LinuxTcl

PerspecSystem VerifierARMRISC-V

Product Engineer II - Memory IP

Mid2+ yrsVerilogRTLDDRLPDDR

Lead Design Engineer - Physical Design

BEIJINGfull-time4d ago

Senior3+ yrsPerlC shellTCLMakefile

Senior10–15 yrsDFTRTLScan insertionLEC

Principal Application Engineer

PUNE 05on-sitefull-time4d ago

Mid4–7 yrsJavaJSspring bootPerl

GYEONGGI-DO (Seoul)4d ago

AMBACHIACEAXI

Lead Software Engineer - AI/LLM for Virtuoso

MidPythonC++MLLLM

SystemVerilogVerilogCC++

Senior12–16 yrsC++TclUnixdata-structures

Applied ML – Functional Verification Engineer

SAN JOSEon-sitefull-time$115k – $213k4d ago

Senior4+ yrsJasperXceliumIMCVerilog

Lead Application Engineer

PUNE 054d ago

GainsightSalesforceCRM

Photonics Engineer

HSINCHU 05full-time4d ago

Mid3+ yrsVerilog-AC++PythonSKILL

Account Executive

PUNE 05hybrid4d ago

Mid3+ yrsFEACFDmultiphysicsCAE

Senior12+ yrsSV/UVMUVMSystem Verilog

Applied ML – Functional Verification Engineer

SAN JOSEon-sitefull-time$154k – $286k4d ago

Senior5+ yrsFormalSV/UVMOVMVerilog

TAVAGNACCO 01on-site4d ago

HSINCHUon-sitefull-time4d ago

Senior10+ yrsCC++Spectre

Mid2+ yrsC++scripting languagescapacitance extractiondevice modeling

HSINCHUfull-time4d ago

Software Intern

SAN JOSEinternship$32k – $59k/hr4d ago

CC++PythonPerl

Strategic Sourcing Specialist

SAN JOSEfull-time$144k – $268k4d ago

Senior15+ yrs

Senior8+ yrsUVMSystemVerilogVerilogDDR

Senior12+ yrsVerilogSystemVerilog

Lead Customer Service Engineer

PUNE 05full-time4d ago

Senior8–10 yrsLinuxVires VTDIPG CarmakerScaner

IT- Sr Systems Engineer (Boomi)

Senior7+ yrsDell Boomi AtomSphereBoomiBoomi AI Agent BuilderJava 17

ZHUBEI 01full-time4d ago

2–5 yrsC++EDASIPI

Senior7–11 yrsC++PythonUNIXLINUX

PRINCIPLE SOFTWARE ENGIREER

Mid4+ yrsVerilogHVLSVSpecman e

Senior Principal Functional Verification Engineer - Applied ML

PETAH TIKVAon-sitefull-time4d ago

Senior10+ yrsFormalSV/UVMOVMEDA

PRINCIPLE SOFTWARE ENGINEER

Senior6+ yrsCC++AMBAPCIe

ZHUBEI 014d ago

CC++Python

Lead Customer Service Engineer

PUNE 05full-time4d ago

Senior8–10 yrsVires VTDIPG CarmakerScanerCarla

Lead Software Engineer ( Verification )

Mid5–8 yrsSystem VerilogSpecman eVHDLVerilog

Lead Customer Engagement Engineer - Voltus

VoltusCelsiusTclPython

SAN JOSEon-sitefull-time$115k – $213k4d ago

Lead Analog IC Designer

Senior3+ yrsCMOSSerDesI/ODriver

ATE Test Engineering Architect

SAN JOSEon-sitefull-time$179k – $332k4d ago

Senior8–12 yrsATECP/FTAdvantest 93KDFT

Senior4–8 yrsSystemVerilogUVMCC++

PUNE 04full-time4d ago

Foundry Virtuoso Engineer

SHANGHAI 08full-time4d ago

3+ yrsVirtuosoPCells

Mixed Signal IP - Senior Program Manager

2 Locationsfull-time$118k – $218k4d ago

Seniormixed-signal IP designSoC developmentanalog designdigital design

Inside Sales Representative

HOME MIfull-time4d ago

Salesforce.comCPQOfficeExcel

Principal Product Engineer - Innovus+

Senior5+ yrsInnovusFusion CompilerIC Compiler IILarge Language Models

Product Validation Engineer II

PUNE 04on-sitefull-time4d ago

SeniorCPythonDSPaudio codecs

Foundry Virtuoso Engineer

SHANGHAI 08on-sitefull-time4d ago

Mid3+ yrsVirtuosoPCellsPDK

Lead Customer Engagement Engineer- Liberate

Product Engineer II -EMX

EMXQuantusVoltusTempus

Customer Engagement Engineer - Pegasus

AUSTINfull-time4d ago

SeniorSV-UVMUVMCARM

Pegasus Verification SystemDRCLVSFILL

Lead Product Engineer - Genus & Innovus

SHANGHAIon-site4d ago

GenusInnovusRTL synthesisfloorplanning

Data Warehouse Engineer

SAN JOSEon-sitefull-time$102k – $189k4d ago

Senior7+ yrsSQLSQL ServerOracleAzure Data Factory

Design Engineering Architect

Senior8+ yrsCAD toolsSERDESPLLClock Distribution

Senior8+ yrsSERDESCMOSDriverReceiver

Executive, Business Development – Horizontals (India, ASEAN, and Pacific)

HOME SINGAPOREfull-time4d ago

Sales Account Executive

Mid5–10 yrsStrategic Selling

NEWCASTLE 01on-sitefull-time4d ago

Senior4+ yrsC++C++14C++17QT

Senior10+ yrsSOC EmulationSOC AccelerationHybrid solutionUVM

Senior Data Operations Manager

SAN JOSEfull-time$137k – $254k4d ago

Senior10–12 yrsExcelSQLSFDCSAP

Software Engineer II - Compiler/LLVM

Mid2+ yrsCC++LLVMGCC

Senior8+ yrsSERDESCMOSDriverReceiver

Lead Digital Verification Engineer

BEIJING4d ago

2 Locationson-sitefull-timeCA$90k – CA$166k4d ago

SeniorSystemVerilogUVMPythonPerl

Lead Application Engineer – Digital Verification

HO CHI MINH CITY 02on-sitefull-time4d ago

Senior5–10 yrsUVMSystemVerilogVerilogVHDL

Senior8+ yrsCMOSSERDESPLLVoltage Regulators

Senior3+ yrsC++Pythoncomputational geometrygraph algorithm

Customer Service Engineer

PUNE 05on-sitefull-time4d ago

Mid2–3 yrsVires VTDIPG CarmakerScanerCarla

Lead Product Engineer - Innovus

GYEONGGI-DO (Seoul)4d ago

InnovusICCP&R techfile

Senior5+ yrsCMOSSERDESCAD tools3nm FinFET CMOS

Principal Application Engineer

Senior10+ yrsSynthesisPnRSTAMachine Learning

Lead Application Engineer - Design Verification

YOKOHAMAon-sitefull-time4d ago

Mid4–6 yrsVerilogVHDLSystem VerilogHDL simulators

Contracts Program Manager

7 Locationson-sitefull-time4d ago

Microsoft Office