Proficient in RTL coding, datapath designs, complex FIFO design Strong knowledge on complete design flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, CLP, Synth and trial PnR Good experience of micro architecture, design, synthesize for a complex SerDes IP in various technology nodes. Desired Protocols knowledge – USB, PCie, MIPI(DPHY), HDMI/Display Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits Good understanding of working with signal processing IPs in terms of knowing calibrations, plls, dividers.