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Samsung Electronics

Lead SOC RTL Design Engineer

LocationIndia
Typefull-time
SeniorityLead
Experience9–12 yrs
Company size10,000+ people
First seenOct 6, 2026 · 5d ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
Must have11
9-12 years of solid experience in SoC IP design & SoC Subsystem Designs
Experience with High Speed & Low Speed Protocol concepts
Experience with SPI/I2C/I3C/UART/PWM all Low Speed IP’s and design
Experience in managing and lead teams of 4-5 Engineers
Architectural level experienced with defining block, sub-system at SOC level
Understanding of interconnect protocols like AXI/AHB/APB concepts
Working knowledge of Lint, CDC, UPF, VCLP, DFT, Power and Clock Flow
Good understanding of the design timing closure and verification debug
Manage SoC dependencies, planning and tracking of all front-end design related tasks
Should possess effective communication and leadership skills
B.Tech/B.E/M.Tech/M.E
Nice to have1
Experience in either UCIe/Ethernet/UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocol
Eligibility1
Equal Employment Opportunity statement
Skills
SPI
I2C
I3C
UART
PWM
UCIe
Ethernet
UFS
AXI
AHB
APB
Lint
CDC
UPF
VCLP
DFT
SoC
Position Summary
Role and Responsibilities
About Samsung Semiconductor India Research (SSIR)
With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.
As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.
Roles and Responsibilities
· 9-12 years of solid experience in SoC IP design & SoC Subsystem Designs
· Experience with High Speed & Low Speed Protocol concepts
· Experience with SPI/I2C/I3C/UART/PWM all Low Speed IP’s and design
· Added advantage for experience in either UCIe/ Ethernet/ UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocol
· Experience in managing and lead teams of 4-5 Engineers
· Architectural level experienced with defining block, sub-system at SOC level
· Understanding of interconnect protocols like AXI/AHB/APB concepts
· Working knowledge of Lint, CDC, UPF, VCLP, DFT, Power and Clock Flow
· Good understanding of the design timing closure and verification debug
· Manage SoC dependencies, planning and tracking of all front-end design related tasks
· Should possess effective communication and leadership skills
Experience – 9 to 12 Years
Qualifications
•
B.Tech/B.E/M.Tech/M.E
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
Skills and Qualifications
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