Principal Formal Verification Engineer
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Before you apply
LocationBengaluru, Karnataka, India
Typefull-time
SeniorityLead
Experience10+ yrs
DepartmentASIC Engineering
Company size1,001–5,000 people
PostedNov 5, 2026 · 2d ago
Verified live7h ago
At a glanceSummarised by Seekless from the posting.
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field
10 years of experience in formal verification, functional verification, or related semiconductor verification roles
Strong understanding of digital design fundamentals, RTL design, and verification concepts
Hands-on experience with formal verification tools and methodologies
Strong knowledge of SystemVerilog, assertions, and verification techniques
Experience verifying complex protocols, control logic, and SoC or subsystem-level designs
Good debugging and analytical problem-solving skills
Experience leading technical efforts or mentoring team members
Strong communication and cross-functional collaboration skills
Experience with industry-standard formal tools such as JasperGold, VC Formal, or equivalent
Knowledge of AMBA protocols such as AXI, AHB, or APB
Familiarity with low-power verification, CDC, RDC, or equivalence checking
Experience in scripting using Python, Perl, Tcl, or shell
Exposure to emulation, simulation, and overall verification lifecycle is a plus
Prior experience in high-speed interconnect, networking, PCIe, CXL, DDR, or similar domains is an advantage
Skills
SystemVerilog
Python
Perl
Tcl
JasperGold
VC Formal
PCIe
CXL
DDR
AMBA
AXI
AHB
APB
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Formal Verification Engineer
Role Overview
We are looking for a Principal Formal Verification Engineer with 10+ years of experience to lead formal verification efforts for complex semiconductor and silicon designs. This role will be responsible for driving verification strategy, improving design quality, and mentoring engineers while working closely with design, architecture, and validation teams.
Key Responsibilities
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Lead formal verification activities for block-level and subsystem-level designs.
•
Define formal verification plans, methodologies, and closure criteria for complex digital designs.
•
Develop and execute formal verification environments, assertions, properties, and checkers.
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Collaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.
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Identify functional corner cases, protocol issues, and design bugs early in the development cycle.
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Drive bug triage, root-cause analysis, and resolution with cross-functional teams.
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Improve verification productivity through reusable flows, automation, and best practices.
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Mentor and guide junior verification engineers and contribute to team capability building.
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Support project planning by estimating verification effort, tracking progress, and highlighting risks.
Required Qualifications
•
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
•
10 years of experience in formal verification, functional verification, or related semiconductor verification roles.
•
Strong understanding of digital design fundamentals, RTL design, and verification concepts.
•
Hands-on experience with formal verification tools and methodologies.
•
Strong knowledge of SystemVerilog, assertions, and verification techniques.
•
Experience verifying complex protocols, control logic, and SoC or subsystem-level designs.
•
Good debugging and analytical problem-solving skills.
•
Experience leading technical efforts or mentoring team members.
•
Strong communication and cross-functional collaboration skills.
Preferred Qualifications
•
Experience with industry-standard formal tools such as JasperGold, VC Formal, or equivalent.
•
Knowledge of AMBA protocols such as AXI, AHB, or APB.
•
Familiarity with low-power verification, CDC, RDC, or equivalence checking.
•
Experience in scripting using Python, Perl, Tcl, or shell.
•
Exposure to emulation, simulation, and overall verification lifecycle is a plus.
•
Prior experience in high-speed interconnect, networking, PCIe, CXL, DDR, or similar domains is an advantage.
Legal
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.