As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr. DFT Engineers.
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Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.
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Create test vectors or oversee their creation.
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Collaborate with physical design team to close timing in DFT mode.
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Sign-off DFT requirements are being met.
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Work with testing team to bring-up test patterns on silicon.
Requirements
Requirements
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Minimum Qualifications
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BE/MS degree in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.
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Hands-on expertise with Mentor/Synopsys test generation tools for large complex designs.
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DFT lead experience for complex SOC TO and Production.
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Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST, SSN.
Nice to have
Preferred Qualifications
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Experience with synthesis, STA and back-end implementation flows.
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Familiar with Tessent shell flow for DFT instruments insertion include MBIST, IJTAG, SSN, BSCAN, OCC etc.
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Solid Lab and test floor bring-up and debug experience.