We are seeking an experienced Analog Design Engineer with 12-18 years of expertise in high-performance PLL and clocking solutions to join our product development team. The candidate will lead the design and development of advanced clock generation, distribution, synchronization, and timing circuits for next-generation SoCs and mixed-signal products, driving innovations from architecture definition through silicon validation and production.
Key Qualifications
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12+ years of experience in analog/mixed-signal IC design with strong expertise in PLL and clocking architectures.
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Deep transistor-level design experience of PLL building blocks including VCOs, charge pumps, phase/frequency detectors (PFDs), loop filters, clock buffers, bandgap references, current references, OPAMPs, and LDOs.
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Strong understanding of jitter, phase noise, clock synchronization, timing recovery, EMC/ESD, reliability, and silicon robustness.
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Hands-on experience with analog design and verification tools such as Cadence Virtuoso, ADE, Spectre/SPICE, and related EDA environments.
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Experience with silicon characterization, validation, yield improvement, and ATE characterization.
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Strong knowledge of advanced CMOS/FinFET technologies and analog layout considerations.
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Proven ability to lead technical reviews, debug silicon issues, and mentor junior engineers.
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Experience with high-speed SerDes, Ethernet PHYs, or timing-intensive mixed-signal systems is an added advantage.
Key Responsibilities
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Architect, design, and verify high-performance PLL, clock generation, clock distribution, and synchronization circuits for advanced semiconductor products.
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Own end-to-end analog design execution including specification definition, transistor-level implementation, performance verification, and silicon bring-up.
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Develop innovative analog circuit solutions to optimize jitter, phase noise, power consumption, and overall system performance.
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Work closely with system, digital, layout, validation, and product engineering teams to define interfaces, calibration methodologies, and verification strategies.
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Drive reliability, EMC/ESD compliance, silicon characterization, and yield improvement activities.
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Lead technical decision-making, conduct design reviews, and provide mentorship to junior engineers while contributing to the overall analog design methodology and roadmap.