IC Design Engineer (STA/ Synthesis)
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Before you apply
Salary$144k – $230k
LocationUSA-CA San Jose Innovation Drive; USA-CA Irvine Alton Parkway Bldg 2; USA-Allentown-1110 American Parkway NE; USA-Colorado-Fort Collins-4380 Ziegler Road; USA-CO Broomfield
Typefull-time
SeniorityLead
Experience7+ yrs
EquityIncluded
Company size10,000+ people
PostedOct 30, 2026 · 1w ago
Verified live3d ago
At a glanceSummarised by Seekless from the posting.
Lead STA/Synthesis engineer
Develop and validate timing constraints for intricate SoC designs
Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus)
Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence) for high speed, complex digital and mixed signal blocks
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties
Conduct pre-route timing checks and quality of results (QoR) analysis
Automate timing analysis processes using scripting languages such as Tcl or Perl
Provide guidance on clock tree synthesis and optimization for energy-efficient designs
Ensure compliance with timing signoff checklists and criteria
Generate timing ECOs for timing closure
Drive timing closure for complex IP and ASIC blocks
Experience with high-complexity silicon in advanced technology nodes
Familiarity with timing constraint development for hierarchical designs
Knowledge of clock tree planning and implementation for SoCs
Experience with timing ECO creation and final timing signoff
Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl)
Proficiency in using synthesis and audit tools (DC-T, Genus, Fishtail, VCLP, Formality)
Strong understanding of ASIC design flows, including RTL and place-and-route
Excellent problem-solving skills and attention to detail
Effective communication and teamwork abilities
Ability to work independently in a fast paced, cross geographical environment
At a minimum Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 7+ years of related experience
Direct or indirect experience with RTL/Design is a plus
Post-graduate coursework is highly desirable
Broadcom is proud to be an equal opportunity employer
Will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law
Will also consider qualified applicants with arrest and conviction records consistent with local law
Skills
PrimeTime
Tempus
Tcl
Perl
DC-T
Genus
Fishtail
VCLP
Formality
Benefits
Health insurance
Dental insurance
Vision insurance
401(k)
Employee stock purchase plan
Employee assistance program
Paid holidays
Paid sick leave
Paid vacation
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Job Description:
Broadcom is looking for a lead STA/ Synthesis engineer. In this role, you will be contributing to constraint development, constraint validation, synthesis, audits (CDC, RDC, Static Equivalence, Low Power) and timing closure of mission critical IP and ASIC blocks in advanced technology nodes
Responsibilities
Responsibilities Include:
•
Develop and validate timing constraints for intricate SoC designs.
•
Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus)
•
Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence) for high speed, complex digital and mixed signal blocks
•
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
•
Conduct pre-route timing checks and quality of results (QoR) analysis.
•
Automate timing analysis processes using scripting languages such as Tcl or Perl.
•
Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
•
Ensure compliance with timing signoff checklists and criteria.
•
Generate timing ECO’s for timing closure
•
Drive timing closure for complex IP and ASIC blocks
Requirements
Qualifications:
•
Experience with high-complexity silicon in advanced technology nodes.
•
Familiarity with timing constraint development for hierarchical designs.
•
Knowledge of clock tree planning and implementation for SoCs.
•
Experience with timing ECO creation and final timing signoff.
•
Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).
•
Proficiency in using synthesis and audit tools (DC-T, Genus, Fishtail, VCLP, Formality)
•
Strong understanding of ASIC design flows, including RTL and place-and-route.
•
Excellent problem-solving skills and attention to detail.
•
Effective communication and teamwork abilities.
•
Ability to work independently in a fast paced, cross geographical environment.
•
Direct or indirect experience with RTL/ Design is a plus
•
At a minimum Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 7+ years of related experience. At this level post-graduate coursework is highly desirable
Compensation and Benefits
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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