Define and implement hardware architectures optimized for AI inference SOC’s
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Contribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO’s
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Own features end-to-end: specification → RTL → integration → synthesis → debug
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Collaborate with physical design teams on synthesis, timing closure, and power optimization.
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Collaborate with verification team to ensure design correctness.
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Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.
Requirements
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Required Qualifications
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7+ years of experience in ASIC/SoC RTL design
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Strong Verilog/SystemVerilog coding skills
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Solid understanding of synthesis, timing, and power analysis
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Experience with Lint/CDC/RDC flows
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Strong debugging and root-cause analysis capability