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CA
Cadence
Sr Principal Design Engineer
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Location
2 Locations
Type
full-time
Company size
10,000+ people
First seen
2w ago
Last seen
5d ago
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Requirements
Experience: 10- 15 years
Location - Bangalore/Pune/
Responsibilities
Responsibilities:
· Complete DFT ownership of projects including:
•
Test architecture definition.
•
Identifying and implementing RTL changes for DFT.
•
Performing scan insertion, LEC checks, low power CLP checks.
•
Developing timing constraints for test mode timing closure.
•
Scan and ATPG for different fault models.
•
Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
•
IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
•
Running zero delay and timing simulations and debugging on all the above aspects.
•
Supporting post silicon bring up.
•
Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
•
Experience working on very high speed and low power designs.
We’re doing work that matters. Help us solve what others can’t.
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