IN
IntelSecurity Hardware Integration Engineer
LocationIsrael, Haifa; Israel, Petah-Tikva
Work modehybrid
Typefull-time
SenioritySenior
Experience5+ yrs
Company size10,000+ people
PostedOct 11, 2026 · 2d ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field
5+ years of experience in RTL development, SoC design, or hardware security integration
Proficient in Verilog/SystemVerilog RTL, IP integration, bus protocols (AXI/AHB/NoC); lint, CDC, synthesis, DV flows
Expertise in roots of trust, TEEs, secure boot/firmware, crypto IP, side-channel mitigations
Fuse/OTP provisioning, supply-chain security, multi-tenant cloud isolation
Skills
Verilog
SystemVerilog
AXI
AHB
NoC
Root of Trust
TEE
secure boot
crypto IP
side-channel mitigations
fuse
OTP provisioning
supply-chain security
multi-tenant cloud isolation
Job Details:
Job Description:
Join us to help build the next generation of AI hardware solutions. You will be part of a team developing cutting-edge HW for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads.
We are continuously developing modern and effective working methods, including hands-on adoption of AI tools throughout the chip development flow. The environment is fast-paced and intellectually stimulating.
Your Mission: Integrate hardware security IP into the SoC/die and define the HW security architecture protecting a large-scale data center’s compute, network, and control infrastructure.
Responsibilities
Responsibilities:
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Integrate third-party and internal HW security IP (Root of Trust, crypto engines, HSMs, TRNG, key vaults) into the die; write and own the RTL/integration code wiring these units into the SoC.
•
Author RTL for security units, glue logic, fuse/OTP interfaces, and bus/fabric (AXI/AHB/NoC) connections; manage clock/reset/power domains and CDC.
•
Develop integration test benches, run lint/CDC/synthesis-readiness checks, and support DV/verification of the embedded security IP.
•
Architect platform Root of Trust, secure boot, attestation, and confidential computing (TDX/SGX/SEV-equivalent) across the server fleet.
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Threat-model the full stack (silicon, firmware, BMC, supply chain) and define HW mitigations against physical and side-channel attacks.
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Drive secure key management, debug-lockdown, fuse provisioning, and crypto offload for tenant isolation at scale.
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Collaborate closely with architecture, design verification, physical design, firmware, and platform teams throughout the development cycle.
Qualifications:
•
B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
•
5+ years of experience in RTL development, SoC design, or hardware security integration.
•
Proficient in Verilog/SystemVerilog RTL, IP integration, bus protocols (AXI/AHB/NoC); lint, CDC, synthesis, DV flows.
•
Expertise in roots of trust, TEEs, secure boot/firmware, crypto IP, side-channel mitigations.
•
Plus: fuse/OTP provisioning, supply-chain security, multi-tenant cloud isolation.
Job Type:
Experienced Hire
Shift:
Shift 1 (Israel)
Primary Location:
Israel, Haifa
Additional Locations:
Israel, Petah-Tikva
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
*