Senior NVM Designer
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Before you apply
SalaryNo pay range posted
LocationPalo Alto, CA
Work modeon-site
Typefull-time
SenioritySenior
Experience5–10 yrs
DepartmentResearch & Advanced Development, Non-Volatile Memory
Company size51–200 people
PostedAug 5, 2026 · 3mo ago
Verified live3d ago
May no longer be actively hiring
Posted by the company on Aug 5, 202666% of this company's open roles have been listed for 90+ daysNo pay range listed, though California requires one
At a glanceSummarised by Seekless from the posting.
Ph.D. or MS degree in EE or related 5-10+ years industrial experience
Hands-on experience in NVM embedded or NVM product design and verification
Hands-on experience in NVM full chip circuit simulation setup, debugging, and verification
Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling
Familiar and hands-on experience some or all memory circuit block design: decoder, high voltage switches, charge pumps, HV and LV regulator, bandgap, high performance low power sense amp, monitoring, and BIST capability
Good understanding & knowledge of semiconductor device physics, and advanced process technology
Experienced in multiple generations NVM tapeout activities, layout supervision, chip planning, silicon debugging
Excellent communication skills, ability to work well across multi-functional teams
Fluent in all major CAD tools: SPICE, Cadence, Verilog simulation software
Must be a self-starter, detail-oriented, and team player
Some knowledge of scripting such as Python
Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.
Skills
Python
Verilog-A
System Verilog
SPICE
Cadence
Verilog
About the company
Mythic was founded in 2012 by University of Michigan researchers Mike Henry and Dave Fick, who set out to answer a simple question: what if a chip worked the way the human brain does? That first-principles thinking became analog compute-in-memory—an architecture that processes data where it lives instead of shuttling it back and forth across power-hungry pathways. Today, that architecture is proving its value. Mythic is the only analog compute-in-memory platform delivering 100x efficiency gains for the innovators who need AI inference at scale without the unsustainable energy cost, with technology proven across data center, automotive, robotics, and defense applications. Backed by an oversubscribed $125M raise from investors including Honda, Lockheed Martin, SoftBank, and DCVC, we’re scaling toward a 1,024-chiplet architecture built for the largest LLM workloads in the data center—taking on the GPU status quo directly. We don’t sell what’s coming. We sell proven technology that works today, built on a fundamentally different approach to computing that we’ve been refining for over a decade. Intelligence is inevitable. How we get there is a choice. And Mythic is proving that power and efficiency were never a tradeoff to begin with.
What you’ll do
•
Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available NVM technologies from foundries
•
Involve in NVM architecture for optimum performance and area
•
Design and verify the new circuits to handshake with the analog computation blocks
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Design, optimize and verify the NVM circuits including and not limited to high voltage generator block, x-path, y-path, test and peripheral circuits
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Participate in RNM and functional model of NVM circuits for verification
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Responsible for verifying the functional blocks and full chip level interfacing with NVM design
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Work closely with the validation engineers to expedite the silicon evaluation process
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Work closely with backend teams for the production qualification releases
What you’ll bring
•
Ph.D. or MS degree in EE or related 5-10+ years industrial experience
•
Hands-on experience in NVM embedded or NVM product design and verification
•
Hands-on experience in NVM full chip circuit simulation setup, debugging, and verification
•
Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling
•
Familiar and hands-on experience some or all memory circuit block design: decoder, high voltage switches, charge pumps, HV and LV regulator, bandgap, high performance low power sense amp, monitoring, and BIST capability
•
Good understanding & knowledge of semiconductor device physics, and advanced process technology
•
Experienced in multiple generations NVM tapeout activities, layout supervision, chip planning, silicon debugging
•
Excellent communication skills, ability to work well across multi-functional teams
•
Fluent in all major CAD tools: SPICE, Cadence, Verilog simulation software
•
Some knowledge of scripting such as Python
•
Must be a self-starter, detail-oriented, and team player
At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.
Legal
Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.