* Participate in the architectural definition and micro-architecture development of SoC blocks and sub-systems.
* Perform RTL design and coding (Verilog/SystemVerilog) for various digital blocks, ensuring adherence to design specifications and best practices.
* Conduct extensive design verification activities, including testbench development, simulation, and debugging, to achieve functional correctness.
* Collaborate with verification engineers to define test plans, coverage goals, and resolve design issues.
* Execute and analyze various front-end design flows, including linting, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and formal verification.
* Perform synthesis and timing analysis (STA) to meet performance targets and ensure timing closure.
* Work closely with backend teams during physical design implementation and post-layout verification.
* Contribute to documentation of design specifications, micro-architecture, and verification plans.
* Participate in design reviews and provide technical feedback.
* Identify and implement opportunities for design optimization in terms of area, power, and performance.