Specific skills & knowledge
• Bachelor or Master in Electronics Engineering and specialization in VLSI domain.
• 5-8 years of hands-on experience in SoC and IP level Synthesis, UPF, formal verification, floor plan, power plan, IO ring, Place & Route, DRC, ERC, LVS, ESD analysis and defining analog / digital interface
•Scope of the work would cover STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few)
• Proven experience in delivering physical implementation closure methodology of mixed signal SoC with high speed PHYs, IOs, PMU IP etc. closing analog / digital interfaces timing & signal integrity issues
• Experience in Cadence tools, low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project
• Experience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on time
• Ability to use scripting languages / automation of Physical Implementation methodology creation and deployment
• Should have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player.
• Excellent communication skills with proven experience in international relationships