We are seeking a highly skilled and experienced STA Methodology Engineer to join our CTO-DE-FDIP-Logic Libraries team. In this role, you will be responsible for benchmarking various logic libraries across multiple technology nodes (40nm, 14nm, 10nm, 7nm, 5nm) using synthesis and PNR-based flows on real-world chips and blocks. You will collaborate closely with Timing Methodology and Signoff teams to ensure robust and efficient STA methodologies.
Key Responsibilities:
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Benchmark logic libraries across advanced technology nodes using synthesis and PNR flows.
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Collaborate with cross-functional teams to validate and refine timing constraints.
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Develop and maintain benchmarking frameworks for constraint validation and STA methodology evaluation.
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Perform comprehensive STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk analysis using Logic Libraries Integration flow checks.
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Contribute to the development and automation of STA flows and methodologies.
Required Qualifications:
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Bachelor’s or Master’s degree in Electrical or Electronics Engineering.
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10–12 years of hands-on experience in STA, with proven tape-out experience as a block owner or lead.
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Deep understanding of STA concepts, timing constraints, and closure methodologies at both block and SoC levels.
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Proficient in handling timing-related issues such as DRCs, annotation, multivoltage flows, noise, and crosstalk.
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Strong collaboration skills and ability to work across teams to drive methodology improvements.
Preferred Skills:
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Proficiency in Python scripting.
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Overview/understanding of AI/GenAI would be added advantage.
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Experience in developing or enhancing STA flow automation.
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Familiarity with industry-standard EDA tools and flows.
Soft Skills:
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Self-motivated with a proactive approach to problem-solving.
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Strong communication and interpersonal skills.
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Ability to work independently and as part of a global team.