Front-End CAD Engineer
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Before you apply
LocationHardware Engineering, Cupertino, CA
Work modeon-site
Typefull-time
SenioritySenior
DepartmentHardware
Company size501–1,000 people
PostedJan 18, 2025 · 1y ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
Experience developing and maintaining front-end IC design flows, including scripting and EDA tool configuration
Proficiency with key verification tools: RTL simulation, static checks (lint/CDC/RDC), formal tools and low power tools
Ability to automate and optimize CAD workflows for chip design verification
Ability to interface with EDA vendors as well as internal users, identify internal needs and priorities and bring in relevant capabilities
A can-do attitude and velocity of going from a problem sighting to a deployable solution
Hands-on RTL design experience, including ownership of a design block to validate CAD methodologies
Setting up and maintaining front-end IC design flows
Working directly with Synopsys and Cadence R&D, sales and field support teams
Working for other chip companies (i.e. Nvidia, Intel, AMD, Qualcomm, Marvell, Broadcom) or an internal chip team at a hyperscaler
Skills
RTL simulation
low power checker
static RTL checkers
Lint
CDC
RDC
SDC
DFT
formal verification
property checkers
equivalence checkers
Synopsys
Cadence
RTL design
Benefits
Health insurance
Dental insurance
Vision insurance
Housing subsidy
Meal benefit
Relocation assistance
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Key responsibilities
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Own and manage Etched’s front-end CAD environment including build flows, tool-specific flows and tool installation and configuration.
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Evaluate, deploy, and sustain front-end tools including but not limited to: RTL simulator, low power checker, static RTL checkers such as Lint, and CDC/RDC/SDC/DFT, and formal verification (both property and equivalence) checkers.
•
Configure and manage project execution dashboard.
You may be a good fit if you have
•
Experience developing and maintaining front-end IC design flows, including scripting and EDA tool configuration.
•
Proficiency with (at least some) key verification tools: RTL simulation, static checks (lint/CDC/RDC), formal tools and low power tools.
•
Ability to automate and optimize CAD workflows for chip design verification.
•
Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in the relevant capabilities
•
A can-do attitude and velocity of going from a problem sighting to a deployable solution.
•
(Bonus) Hands-on RTL design experience, including ownership of a design block to validate CAD methodologies.
Strong candidates may also have experience
•
Setting up and maintaining front-end IC design flows.
•
Working directly with Synopsys and Cadence R&D, sales and field support teams.
•
Working for other chip companies (i.e. Nvidia, Intel, AMD, Qualcomm, Marvell, Broadcom) or an internal chip team at a hyperscaler.
Benefits
•
Full medical, dental, and vision packages, with 100% of premium covered
•
Housing subsidy of $2,000/month for those living within walking distance of the office
•
Daily lunch and dinner in our office
•
Relocation support for those moving to Cupertino
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.