PDK Deck Developer
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Before you apply
LocationNoida
SeniorityLead
Experience15+ yrs
Company size10,000+ people
PostedOct 23, 2026 · 1w ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
15+ years experience with PDK Physical Verification rule deck development/support and/or support of Physical verification rule decks/runsets - DRC/LVS/ERC/PERC/FILL or Parasitic and EMIR rule decks
In depth knowledge of foundry based and EDA tools based process variation formats e.g. ICT, IRCX etc. and understanding of latest EMIR & EM challenges
Experience with Calibre SVRF/TVF rule deck coding OR Cadence PVS/Assura rule deck coding
Experience with some of the following tools: Calibre, CalibreXRC, Assura, Assura RF, Cadence PVS, Synopsys ICV, Virtuoso, Cadence QRC, StarRCXT, Voltus, Redhawk
BE/B.Tech/ME/M.Tech in Electrical or Electronics Engineering or other similar discipline
15+ years of relevant experience
Experience with at least 2 of the following programming languages: perl, python, skill, shell, c/c++, tcl
Skills
Calibre
CalibreXRC
Assura
Assura RF
Cadence PVS
Synopsys ICV
Virtuoso
Cadence QRC
StarRCXT
Voltus
Redhawk
perl
python
skill
shell
c/c++
tcl
AI tools
LLM
Calibre AI
Virtuoso AI
ICT
IRCX
Job Summary
•
Manage and lead Process Design Kit (PDK) Physical Verification (PV) team.
•
PDK PV manager will also create Sciforma plans, PDK planning and release documents as per BCaM7 way of working. Candidate will be responsible to drive PDK PV testing, customer support and tool evaluations.
•
Selected candidate will be responsible for PDK PV development methods and procedures for continuous quality improvement and refine PDK PV specifications and planning.
•
Selected candidate needs to continuously drive PDK PV productivity enhancements and efficiency alignment across technologies using latest AI tools and techniques.
•
Selected candidate needs to work with Cross geographic team to align on way of working and PDK PV release planning alignment. undefined
Job Responsibilities
•
Physical Verification team is responsible for development of Calibre physical verification decks for cmos, FinFET, bulk, SOI, RF, bicmos and powermos technologies including DRC, LVS, PERC, Fill LPE, and shape generation decks and scripts.
•
Development and validation of PV tools and flows using LLM based AI tools, recent EDA AI tools like Calibre AI, Virtuoso AI etc.
•
Development of the Process Design Kit (PDK) infrastructure for PV tools, flows and utilities which includes setups, configurations, integration of technology specific data.
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Responsibilities will include testing, validation, customer support and new tool/methods evaluations, development of methods and procedures for quality improvement, automation of deck/techFiles generation and validation.
Job Qualifications
•
Required experience (15+ yrs) with PDK Physical Verification rule deck development/support and/or support of (1) Physical verification rule decks/runsets - DRC/LVS/ERC/PERC/FILL Or (2) Parasitic and EMIR rule decks
•
In depth knowledge of foundry based and EDA tools based process variation formats e.g. ICT, IRCX etc. and understands latest EMIR & EM challenges.
•
Experience with either - Calibre SVRF/TVF rule deck coding OR Cadence PVS/Assura rule deck coding is a must.
•
Experience with some of the following tools is required: Calibre, CalibreXRC, Assura, Assura RF, Cadence PVS, Synopsys ICV, Virtuoso, Cadence QRC, StarRCXT, Voltus, Redhawk.
•
Experience with at least 2 of the following programming languages is a plus: perl, python, skill, shell, c/c++, tcl.
•
BE/B.Tech/ME/M.Tech in Electrical or Electronics Engineering or other similar discipline with at least 15+ years of relevant experience
About the company
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