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Astera Labs

Principal Package Signal & Power Integrity

Salary$203k – $240k
LocationSan Jose, California, United States
Typefull-time
DepartmentASIC Engineering
Company size1,001–5,000 people
First seen1w ago
Last seen4d ago
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description:
As a Principal Package Signal & Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems.
In this role, you will lead SIPI strategy and execution for products supporting PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. You will partner closely with silicon architecture, SerDes/IP teams, package design, PCB design, hardware validation, manufacturing, substrate vendors, and OSAT partners to optimize signal integrity, power delivery, substrate/interposer routing, bump planning, and system-level electrical performance while balancing cost, manufacturability, reliability, yield, and schedule.
You will also drive SIPI methodology, modeling standards, simulation-to-measurement correlation, and chip–package–board co-design frameworks to enable scalable execution across multiple product lines.
Key Responsibilities
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Define package SIPI architecture and design strategy for high-performance connectivity products, including PCIe 5.0/6.0/7.0, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect.
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Perform package and system-level SI and PI simulations using industry-standard simulation software such as HFSS, SIwave, and Keysight ADS to develop, optimize, and sign off package electrical models, validate package architecture and designs, and ensure robust signal and power integrity across chip–package–board systems.
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Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule.
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Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria.
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Own SIPI simulation and signoff for advanced packaging platforms, including chiplet-based packages, 2.5D/3D integration, silicon interposers, and bridge-based interconnect, by leading simulations for D2D interconnect (e.g., UCIe), multi-die PDN, micro-bump modeling, TSV/interposer modeling, and multi-die CPM co-simulation.
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Define substrate, interposer, and bridge routing guidelines for high-speed SerDes and D2D interfaces, including impedance targets, differential-pair geometry, via/transition optimization, return-current management, shielding, skew control, and crosstalk isolation.
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Establish SIPI modeling standards, design rules, review checklists, automation flows, and signoff methodologies to improve execution efficiency, while mentoring engineers across the organization.
Required qualifications:
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10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products.
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Deep expertise in package SIPI modeling, analysis, optimization, and signoff across the chip–package–board system, for high-speed SerDes, PCIe, CXL, Ethernet, etc.
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Strong experience with PCIe 5.0/6.0, PAM4 SerDes channel design, high-speed S-parameter extraction, package model development, eye-diagram analysis, return/insertion-loss optimization, and crosstalk analysis.
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Proven track record delivering high-performance packages using FCBGA, FCCSP, coreless substrates, advanced organic substrates, chiplet-based packages, 2.5D integration, silicon interposers, or heterogeneous integration platforms.
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Hands-on expertise with EM extraction and SIPI simulation tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools.
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Expert-level knowledge of PDN design, including DC IR drop, AC impedance, target impedance, loop inductance, decoupling optimization, transient response, noise coupling, and chip-package-model methodology.
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Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope).
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Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability.
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Experience leading vendor engagements and managing technical execution through production ramps.
Preferred Qualifications:
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Experience influencing silicon floor planning, bump map definition, SerDes and power-grid planning, package escape strategy, and PCB breakout from a SIPI perspective.
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Experience with automation and scripting for SIPI modeling flow.
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Exposure to Allegro Package Designer (APD) for hands-on substrate editing.
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Knowledge on traditional FCBGA type package and advanced package (chiplet/2.5D/3D) manufacturing and assembly process flows
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Experience with CPO and NPO optical package SIPI design, including high-speed channel modeling between EIC/PIC/optical engine, PDN design, crosstalk/noise analysis, and chip–package–board co-design for optical connectivity applications.
Benefits
The base salary range is $203,000 USD – $240,000 USD. Your base salary will be determined based on location, experience, and employees’ pay in similar positions.
Legal
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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